User manual

Managing the Contents of the FIFO Buffers
9-15 Synchronous Serial Port
9.4 Managing the Contents of the FIFO Buffers
The SDTR is a read/write register (at I/O address FFF0h) that is used to send
data to the transmit FIFO buffer and to extract data from the receive FIFO
buffer.
A word is written to the SDTR by the OUT instruction. When the transmit FIFO
buffer is full, additional writes to the SDTR are ignored. Therefore, your pro-
gram should not write a word for transmission until at least one space is avail-
able in the transmit FIFO buffer. You can set up a transmit interrupt (XINT)
based on the contents of the buffer (using the FT1 and FT0 bits of the SSPCR).
If your program writes words to the buffer only when the buffer is empty, you
can use the transmission complete (TCOMP) bit; when the buffer is empty,
TCOMP = 0.
When the receive FIFO buffer holds data, you can read the received data from
the FIFO buffer through the SDTR (using the IN instruction). You can check
the state of the receive buffer by reading the receive FIFO buffer not empty
(RFNE) bit in the SSPCR, or you can set up a receive interrupt (RINT) based
on the state of the buffer (using the FR1 and FR0 bits of the SSPCR).