User manual

Clock Generator
8-5 On-Chip Peripherals
External Oscillator. CLKIN is the output of an external oscillator, which
is connected to the CLKIN/X2 pin. The X1 pin must be left unconnected.
See Figure 8–2.
Figure 8–2. Using an External Oscillator
’C2xx
X1
CLKIN/X2
No connection
Oscillator
Regardless of the method used to generate CLKOUT1, CLKOUT1 is also
available at the CLKOUT1 pin, unless the pin is turned off by the CLK register
(see Section 8.3).
You can lower the power requirements for the ’C2xx by slowing down or stop-
ping the input clock.
Note:
When restarting the system, activate RS
before starting or stopping the
clock, and hold it active until the clock stabilizes. This brings the device back
to a known state.
8.2.1 Clock Generator Options
The ’C2xx provides four clock modes: divide-by-2 (÷2), multiply-by-1 (×1),
multiply-by-2 (×2), and multiply-by-4 (×4). The
÷2 mode operates the CPU at
half the input clock rate. Each of the other modes operates the CPU at a multi-
ple of the input clock rate and phase locks the output clock with the the input
clock. You set the mode by changing the levels on the DIV1 and DIV2 pins. For
each mode, Table 8–2 shows the generated CPU clock rate and the state of
DIV2, DIV1, the internal oscillator, and the internal phase lock loop (PLL).
Notes:
1) Change DIV1 and DIV2 only while the reset signal (RS
) is active.
2) The PLL requires approximately 2500 cycles to lock the output clock sig-
nal to the input clock signal. When setting the ×1, ×2, or ×4 mode, keep
the reset (RS) signal active until at least three cycles after the PLL has
stabilized.