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Table Of Contents

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Contents
Figures
Tables
Examples
Cautions
Introduction
- TMS320 Family
  - History, Development, and Advantages of TMS320 DSPs
  - Typical Applications for the TMS320 Family
- TMS320C2xx Generation
- Key Features of the TMS320C2xx
Architectural Overview
- ’C2xx Bus Structure
- Central Processing Unit
- Memory and I/O Spaces
- Program Control
- On-Chip Peripherals
- Scanning-Logic Circuitry
Central Processing Unit
- Input Scaling Section
- Multiplication Section
  - Multiplier
  - Product-Scaling Shifter
- Central Arithmetic Logic Section
- Auxiliary Register Arithmetic Unit (ARAU)
  - ARAU and Auxiliary Register Functions
- Status Registers ST0 and ST1
Memory and I/O Spaces
- Overview of the Memory and I/O Spaces
  - Pins for Interfacing to External Memory and I/O Spaces
- Program Memory
  - Interfacing With External Program Memory
- Local Data Memory
  - Data Page 0 Address Map
  - Interfacing With External Local Data Memory
- Global Data Memory
  - Interfacing With External Global Data Memory
- Boot Loader
- I/O Space
  - Accessing I/O Space
- Direct Memory Access Using the HOLD Operation
  - HOLD During Reset
- Device-Specific Information
  - TMS320C203 Address Maps and Memory Configuration
  - TMS320C204 Address Maps and Memory Configuration
Program Control
- Program-Address Generation
- Pipeline Operation
- Branches, Calls, and Returns
- Conditional Branches, Calls, and Returns
- Repeating a Single Instruction
- Interrupts
- Reset Operation
- Power-Down Mode
  - Normal Termination of Power-Down Mode
  - Termination of Power-Down During a HOLD Operation
Addressing Modes
- Immediate Addressing Mode
  - Examples of Immediate Addressing
- Direct Addressing Mode
  - Using Direct Addressing Mode
  - Examples of Direct Addressing
- Indirect Addressing Mode
Assembly Language Instructions
- Instruction Set Summary
- How To Use the Instruction Descriptions
- Instruction Descriptions
  - ABS
  - ABS
  - ADD
  - ADD
  - ADD
  - ADD
  - ADDC
  - ADDC
  - ADDS
  - ADDS
  - ADDT
  - ADDT
  - ADRK
  - AND
  - AND
  - AND
  - APAC
  - APAC
  - B
  - BACC
  - BANZ
  - BANZ
  - BCND
  - BCND
  - BIT
  - BIT
  - BITT
  - BITT
  - BLDD
  - BLDD
  - BLDD
  - BLDD
  - BLDD
  - BLPD
  - BLPD
  - BLPD
  - BLPD
  - CALA
  - CALL
  - CC
  - CC
  - CLRC
  - CLRC
  - CMPL
  - CMPR
  - DMOV
  - DMOV
  - IDLE
  - IN
  - IN
  - INTR
  - LACC
  - LACC
  - LACC
  - LACL
  - LACL
  - LACL
  - LACT
  - LACT
  - LAR
  - LAR
  - LAR
  - LDP
  - LDP
  - LPH
  - LPH
  - LST
  - LST
  - LST
  - LST
  - LT
  - LT
  - LTA
  - LTA
  - LTD
  - LTD
  - LTD
  - LTP
  - LTP
  - LTS
  - LTS
  - MAC
  - MAC
  - MAC
  - MAC
  - MACD
  - MACD
  - MACD
  - MACD
  - MACD
  - MAR
  - MAR
  - MPY
  - MPY
  - MPY
  - MPYA
  - MPYA
  - MPYS
  - MPYS
  - MPYU
  - MPYU
  - NEG
  - NEG
  - NMI
  - NOP
  - NORM
  - NORM
  - NORM
  - OR
  - OR
  - OR
  - OUT
  - OUT
  - PAC
  - POP
  - POP
  - POPD
  - POPD
  - PSHD
  - PSHD
  - PUSH
  - RET
  - RETC
  - ROL
  - ROR
  - RPT
  - RPT
  - SACH
  - SACH
  - SACL
  - SACL
  - SAR
  - SAR
  - SBRK
  - SETC
  - SETC
  - SFL
  - SFR
  - SFR
  - SPAC
  - SPH
  - SPH
  - SPL
  - SPL
  - SPLK
  - SPLK
  - SPM
  - SQRA
  - SQRA
  - SQRS
  - SQRS
  - SST
  - SST
  - SUB
  - SUB
  - SUB
  - SUB
  - SUBB
  - SUBB
  - SUBC
  - SUBC
  - SUBS
  - SUBS
  - SUBT
  - SUBT
  - TBLR
  - TBLR
  - TBLR
  - TBLW
  - TBLW
  - TBLW
  - TRAP
  - XOR
  - XOR
  - XOR
  - ZALR
  - ZALR
On-Chip Peripherals
- Control of On-Chip Peripherals
- Clock Generator
  - Clock Generator Options
- CLKOUT1-Pin Control (CLK) Register
- Timer
- Wait-State Generator
  - Generating Wait States With the READY Signal
  - Generating Wait States With the ’C2xx Wait-State Generator
- General-Purpose I/O Pins
Synchronous Serial Port
- Overview of the Synchronous Serial Port
- Components and Basic Operation
- Controlling and Resetting the Port
- Managing the Contents of the FIFO Buffers
- Transmitter Operation
- Receiver Operation
  - Burst Mode Reception
  - Continuous Mode Reception
- Troubleshooting
Asynchronous Serial Port
- Overview of the Asynchronous Serial Port
- Components and Basic Operation
- Controlling and Resetting the Port
- Transmitter Operation
- Receiver Operation
TMS320C209
- ’C209 Versus Other ’C2xx Devices
- ’C209 Memory and I/O Spaces
- ’C209 Interrupts
  - ’C209 Interrupt Registers
  - IACK Pin
- ’C209 On-Chip Peripherals
Register Summary
- A.1 Addresses and Reset Values
- A.2 Register Descriptions
TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison
- B.1 Using the Instruction Set Comparison Table
  - B.1.1 An Example of a Table Entry
  - B.1.2 Symbols and Acronyms Used in the Table
- B.2 Enhanced Instructions
- B.3 Instruction Set Comparison Table
Program Examples
- C.1 About These Program Examples
- C.2 Shared Program Code
- C.3 Task-Specific Program Code
- C.4 Introduction to Generating Boot Loader Code
Submitting ROM Codes to TI
Design Considerations for Using XDS510 Emulator
- E.1 Designing Your Target System’s Emulator Connector (14-Pin Header)
- E.2 Bus Protocol
- E.3 Emulator Cable Pod
- E.4 Emulator Cable Pod Signal Timing
- E.5 Emulation Timing Calculations
- E.6 Connections Between the Emulator and the Target System
- E.7 Physical Dimensions for the 14-Pin Emulator Connector
- E.8 Emulation Design Considerations
Glossary
Index

Examples

xxv

Contents

Examples

4–1 An Interrupt Service Routine Supporting INT1 and HOLD 4-28. . . . . . . . . . . . . . . . . . . . . . . . .

6–1 RPT Instruction Using Short-Immediate Addressing 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–2 ADD Instruction Using Long-Immediate Addressing 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–3 Using Direct Addressing with ADD (Shift of 0 to 15) 6-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–4 Using Direct Addressing with ADD (Shift of 16) 6-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–5 Using Direct Addressing with ADDC 6-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–6 Selecting a New Current Auxiliary Register 6-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–7 No Increment or Decrement 6-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–8 Increment by 1 6-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–9 Decrement by 1 6-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–10 Increment by Index Amount 6-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–11 Decrement by Index Amount 6-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–12 Increment by Index Amount With Reverse Carry Propagation 6-16. . . . . . . . . . . . . . . . . . . . . .

6–13 Decrement by Index Amount With Reverse Carry Propagation 6-16. . . . . . . . . . . . . . . . . . . . .

C–1 Generic Command File (c203.cmd) C-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C–2 Header File With I/O Register Declarations (init.h) C-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C–3 Header File With Interrupt Vector Declarations (vector.h) C-7. . . . . . . . . . . . . . . . . . . . . . . . . . .

C–4 Implementing Simple Delay Loops (delay.asm) C-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C–5 Testing and Using the Timer (timer.asm) C-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C–6 Testing and Using Interrupt INT1

(intr1.asm) C-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C–7 Implementing a HOLD Operation (hold.asm) C-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C–8 Testing and Using Interrupts INT2

and INT3 (intr23.asm) C-12. . . . . . . . . . . . . . . . . . . . . . . . . .

C–9 Asynchronous Serial Port Transmission (uart.asm) C-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C–10 Loopback to Verify Transmissions of Asynchronous Serial Port (echo.asm) C-14. . . . . . . . . .

C–11 Testing and Using Automatic Baud-Rate Detection on

Asynchronous Serial Port (autobaud.asm) C-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C–12 Testing and Using Asynchronous Serial Port Delta Interrupts (bitio.asm) C-18. . . . . . . . . . . . .

C–13 Synchronous Serial Port Continuous Mode Transmission (ssp.asm) C-20. . . . . . . . . . . . . . . .

C–14 Using Synchronous Serial Port With Codec Device (ad55.asm) C-21. . . . . . . . . . . . . . . . . . . .

C–15 Linker Command File C-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C–16 Hex Conversion Utility Command File C-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

E–1 Key Timing for a Single-Processor System Without Buffers E-8. . . . . . . . . . . . . . . . . . . . . . . . .

E–2 Key Timing for a Single- or Multiple-Processor System With

Buffered Input and Output E-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

E–3 Key Timing for a Single-Processor System Without Buffering (SPL) E-19. . . . . . . . . . . . . . . . .

E–4 Key Timing for a Single- or Multiprocessor-System With

Buffered Input and Output (SPL) E-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .