User manual
Table Of Contents
- Read This First
- Contents
- Figures
- Tables
- Examples
- Cautions
- Introduction
- Architectural Overview
- Central Processing Unit
- Memory and I/O Spaces
- Program Control
- Addressing Modes
- Assembly Language Instructions
- Instruction Set Summary
- How To Use the Instruction Descriptions
- Instruction Descriptions
- ABS
- ABS
- ADD
- ADD
- ADD
- ADD
- ADDC
- ADDC
- ADDS
- ADDS
- ADDT
- ADDT
- ADRK
- AND
- AND
- AND
- APAC
- APAC
- B
- BACC
- BANZ
- BANZ
- BCND
- BCND
- BIT
- BIT
- BITT
- BITT
- BLDD
- BLDD
- BLDD
- BLDD
- BLDD
- BLPD
- BLPD
- BLPD
- BLPD
- CALA
- CALL
- CC
- CC
- CLRC
- CLRC
- CMPL
- CMPR
- DMOV
- DMOV
- IDLE
- IN
- IN
- INTR
- LACC
- LACC
- LACC
- LACL
- LACL
- LACL
- LACT
- LACT
- LAR
- LAR
- LAR
- LDP
- LDP
- LPH
- LPH
- LST
- LST
- LST
- LST
- LT
- LT
- LTA
- LTA
- LTD
- LTD
- LTD
- LTP
- LTP
- LTS
- LTS
- MAC
- MAC
- MAC
- MAC
- MACD
- MACD
- MACD
- MACD
- MACD
- MAR
- MAR
- MPY
- MPY
- MPY
- MPYA
- MPYA
- MPYS
- MPYS
- MPYU
- MPYU
- NEG
- NEG
- NMI
- NOP
- NORM
- NORM
- NORM
- OR
- OR
- OR
- OUT
- OUT
- PAC
- POP
- POP
- POPD
- POPD
- PSHD
- PSHD
- PUSH
- RET
- RETC
- ROL
- ROR
- RPT
- RPT
- SACH
- SACH
- SACL
- SACL
- SAR
- SAR
- SBRK
- SETC
- SETC
- SFL
- SFR
- SFR
- SPAC
- SPH
- SPH
- SPL
- SPL
- SPLK
- SPLK
- SPM
- SQRA
- SQRA
- SQRS
- SQRS
- SST
- SST
- SUB
- SUB
- SUB
- SUB
- SUBB
- SUBB
- SUBC
- SUBC
- SUBS
- SUBS
- SUBT
- SUBT
- TBLR
- TBLR
- TBLR
- TBLW
- TBLW
- TBLW
- TRAP
- XOR
- XOR
- XOR
- ZALR
- ZALR
- On-Chip Peripherals
- Synchronous Serial Port
- Asynchronous Serial Port
- TMS320C209
- Register Summary
- TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison
- Program Examples
- Submitting ROM Codes to TI
- Design Considerations for Using XDS510 Emulator
- E.1 Designing Your Target System’s Emulator Connector (14-Pin Header)
- E.2 Bus Protocol
- E.3 Emulator Cable Pod
- E.4 Emulator Cable Pod Signal Timing
- E.5 Emulation Timing Calculations
- E.6 Connections Between the Emulator and the Target System
- E.7 Physical Dimensions for the 14-Pin Emulator Connector
- E.8 Emulation Design Considerations
- Glossary
- Index
Tables
xxiii
Contents
Tables
1–1 Typical Applications for TMS320 DSPs 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 ’C2xx Generation Summary 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 Program and Data Memory on the TMS320C2xx Devices 2-7. . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Serial Ports on the ’C2xx Devices 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 Product Shift Modes for the Product-Scaling Shifter 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 Bit Fields of Status Registers ST0 and ST1 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 Pins for Interfacing With External Memory and I/O Spaces 4-3. . . . . . . . . . . . . . . . . . . . . . . . .
4–2 Data Page 0 Address Map 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 Global Data Memory Configurations 4-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 On-Chip Registers Mapped to I/O Space 4-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–5 ’C203 Program-Memory Configuration Options 4-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–6 ’C203 Data-Memory Configuration Options 4-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–7 ’C204 Program-Memory Configuration Options 4-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–8 ’C204 Data-Memory Configuration Options 4-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 Program-Address Generation Summary 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Address Loading to the Program Counter 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 Conditions for Conditional Calls and Returns 5-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 Groupings of Conditions 5-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–5 ’C2xx Interrupt Locations and Priorities 5-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–6 Reset Values of On-Chip Registers Mapped to Data Space 5-35. . . . . . . . . . . . . . . . . . . . . . . .
5–7 Reset Values of On-Chip Registers Mapped to I/O Space 5-35. . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Indirect Addressing Operands 6-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 Effects of the ARU Code on the Current Auxiliary Register 6-13. . . . . . . . . . . . . . . . . . . . . . . . .
6–3 Field Bits and Notation for Indirect Addressing 6-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–1 Accumulator, Arithmetic, and Logic Instructions 7-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–2 Auxiliary Register Instructions 7-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–3 TREG, PREG, and Multiply Instructions 7-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–4 Branch Instructions 7-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–5 Control Instructions 7-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–6 I/O and Memory Instructions 7-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–7 Product Shift Modes 7-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–8 Product Shift Modes 7-167. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–1 Peripheral Register Locations and Reset Conditions 8-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–2 ’C2xx Input Clock Modes 8-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–3 ’C2xx Timer Run/Emulation Modes 8-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–4 Setting the Number of Wait States With the ’C2xx WSGR Bits 8-16. . . . . . . . . . . . . . . . . . . . .