User manual

ManualsBrandsTexas Instruments ManualsOtherCalculator TMS320C2XX

131

132

133

134

135

136

137

138

139

140

Table Of Contents

Read This First
Contents
Figures
Tables
Examples
Cautions
Introduction
- TMS320 Family
  - History, Development, and Advantages of TMS320 DSPs
  - Typical Applications for the TMS320 Family
- TMS320C2xx Generation
- Key Features of the TMS320C2xx
Architectural Overview
- ’C2xx Bus Structure
- Central Processing Unit
- Memory and I/O Spaces
- Program Control
- On-Chip Peripherals
- Scanning-Logic Circuitry
Central Processing Unit
- Input Scaling Section
- Multiplication Section
  - Multiplier
  - Product-Scaling Shifter
- Central Arithmetic Logic Section
- Auxiliary Register Arithmetic Unit (ARAU)
  - ARAU and Auxiliary Register Functions
- Status Registers ST0 and ST1
Memory and I/O Spaces
- Overview of the Memory and I/O Spaces
  - Pins for Interfacing to External Memory and I/O Spaces
- Program Memory
  - Interfacing With External Program Memory
- Local Data Memory
  - Data Page 0 Address Map
  - Interfacing With External Local Data Memory
- Global Data Memory
  - Interfacing With External Global Data Memory
- Boot Loader
- I/O Space
  - Accessing I/O Space
- Direct Memory Access Using the HOLD Operation
  - HOLD During Reset
- Device-Specific Information
  - TMS320C203 Address Maps and Memory Configuration
  - TMS320C204 Address Maps and Memory Configuration
Program Control
- Program-Address Generation
- Pipeline Operation
- Branches, Calls, and Returns
- Conditional Branches, Calls, and Returns
- Repeating a Single Instruction
- Interrupts
- Reset Operation
- Power-Down Mode
  - Normal Termination of Power-Down Mode
  - Termination of Power-Down During a HOLD Operation
Addressing Modes
- Immediate Addressing Mode
  - Examples of Immediate Addressing
- Direct Addressing Mode
  - Using Direct Addressing Mode
  - Examples of Direct Addressing
- Indirect Addressing Mode
Assembly Language Instructions
- Instruction Set Summary
- How To Use the Instruction Descriptions
- Instruction Descriptions
  - ABS
  - ABS
  - ADD
  - ADD
  - ADD
  - ADD
  - ADDC
  - ADDC
  - ADDS
  - ADDS
  - ADDT
  - ADDT
  - ADRK
  - AND
  - AND
  - AND
  - APAC
  - APAC
  - B
  - BACC
  - BANZ
  - BANZ
  - BCND
  - BCND
  - BIT
  - BIT
  - BITT
  - BITT
  - BLDD
  - BLDD
  - BLDD
  - BLDD
  - BLDD
  - BLPD
  - BLPD
  - BLPD
  - BLPD
  - CALA
  - CALL
  - CC
  - CC
  - CLRC
  - CLRC
  - CMPL
  - CMPR
  - DMOV
  - DMOV
  - IDLE
  - IN
  - IN
  - INTR
  - LACC
  - LACC
  - LACC
  - LACL
  - LACL
  - LACL
  - LACT
  - LACT
  - LAR
  - LAR
  - LAR
  - LDP
  - LDP
  - LPH
  - LPH
  - LST
  - LST
  - LST
  - LST
  - LT
  - LT
  - LTA
  - LTA
  - LTD
  - LTD
  - LTD
  - LTP
  - LTP
  - LTS
  - LTS
  - MAC
  - MAC
  - MAC
  - MAC
  - MACD
  - MACD
  - MACD
  - MACD
  - MACD
  - MAR
  - MAR
  - MPY
  - MPY
  - MPY
  - MPYA
  - MPYA
  - MPYS
  - MPYS
  - MPYU
  - MPYU
  - NEG
  - NEG
  - NMI
  - NOP
  - NORM
  - NORM
  - NORM
  - OR
  - OR
  - OR
  - OUT
  - OUT
  - PAC
  - POP
  - POP
  - POPD
  - POPD
  - PSHD
  - PSHD
  - PUSH
  - RET
  - RETC
  - ROL
  - ROR
  - RPT
  - RPT
  - SACH
  - SACH
  - SACL
  - SACL
  - SAR
  - SAR
  - SBRK
  - SETC
  - SETC
  - SFL
  - SFR
  - SFR
  - SPAC
  - SPH
  - SPH
  - SPL
  - SPL
  - SPLK
  - SPLK
  - SPM
  - SQRA
  - SQRA
  - SQRS
  - SQRS
  - SST
  - SST
  - SUB
  - SUB
  - SUB
  - SUB
  - SUBB
  - SUBB
  - SUBC
  - SUBC
  - SUBS
  - SUBS
  - SUBT
  - SUBT
  - TBLR
  - TBLR
  - TBLR
  - TBLW
  - TBLW
  - TBLW
  - TRAP
  - XOR
  - XOR
  - XOR
  - ZALR
  - ZALR
On-Chip Peripherals
- Control of On-Chip Peripherals
- Clock Generator
  - Clock Generator Options
- CLKOUT1-Pin Control (CLK) Register
- Timer
- Wait-State Generator
  - Generating Wait States With the READY Signal
  - Generating Wait States With the ’C2xx Wait-State Generator
- General-Purpose I/O Pins
Synchronous Serial Port
- Overview of the Synchronous Serial Port
- Components and Basic Operation
- Controlling and Resetting the Port
- Managing the Contents of the FIFO Buffers
- Transmitter Operation
- Receiver Operation
  - Burst Mode Reception
  - Continuous Mode Reception
- Troubleshooting
Asynchronous Serial Port
- Overview of the Asynchronous Serial Port
- Components and Basic Operation
- Controlling and Resetting the Port
- Transmitter Operation
- Receiver Operation
TMS320C209
- ’C209 Versus Other ’C2xx Devices
- ’C209 Memory and I/O Spaces
- ’C209 Interrupts
  - ’C209 Interrupt Registers
  - IACK Pin
- ’C209 On-Chip Peripherals
Register Summary
- A.1 Addresses and Reset Values
- A.2 Register Descriptions
TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison
- B.1 Using the Instruction Set Comparison Table
  - B.1.1 An Example of a Table Entry
  - B.1.2 Symbols and Acronyms Used in the Table
- B.2 Enhanced Instructions
- B.3 Instruction Set Comparison Table
Program Examples
- C.1 About These Program Examples
- C.2 Shared Program Code
- C.3 Task-Specific Program Code
- C.4 Introduction to Generating Boot Loader Code
Submitting ROM Codes to TI
Design Considerations for Using XDS510 Emulator
- E.1 Designing Your Target System’s Emulator Connector (14-Pin Header)
- E.2 Bus Protocol
- E.3 Emulator Cable Pod
- E.4 Emulator Cable Pod Signal Timing
- E.5 Emulation Timing Calculations
- E.6 Connections Between the Emulator and the Target System
- E.7 Physical Dimensions for the 14-Pin Emulator Connector
- E.8 Emulation Design Considerations
Glossary
Index

Reset Operation

5-35

Program Control

Table 5–6. Reset Values of On-Chip Registers Mapped to Data Space

Name Data-Memory Address Reset Value Description

IMR 0004h 0000h Interrupt mask register

GREG 0005h 0000h Interrupt control register

IFR

0006h 0000h Synchronous data transmit and receive register

Table 5–7. Reset Values of On-Chip Registers Mapped to I/O Space

I/O Address

Name ’C209 Other ’C2xx Reset Value Description

CLK

– FFE8h 0000h CLKOUT1-pin control (CLK) register

ICR – FFECh 0000h Interrupt control register

SDTR – FFF0h xxxxh Synchronous data transmit and receive register

SSPCR – FFF1h 0030h Synchronous serial port control register

ADTR – FFF4h xxxxh Asynchronous data transmit and receive register

ASPCR – FFF5h 0000h Asynchronous serial port control register

IOSR – FFF6h 18xxh I/O status register

BRD – FFF7h 0001h Baud-rate divisor register

TCR FFFCh FFF8h 0000h Timer control register

PRD FFFDh FFF9h FFFFh Timer period register

TIM FFFEh FFFAh FFFFh Timer counter register

WSGR FFFFh FFFCh 0FFFh Wait-state generator control register

Note: An x in an address represents four bits that are either not affected by reset or dependent on pin levels at reset.