TMS320C2xx User’s Guide Literature Number: SPRU127B Manufacturing Part Number: D412008-9761 revision A January 1997 Printed on Recycled Paper
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How to Use This Manual Preface Read This First About This Manual This user’s guide describes the architecture, hardware, assembly language instructions, and general operation of the TMS320C2xx digital signal processors (DSPs). This manual can also be used as a reference guide for developing hardware and/or software applications. In this document, ’C2xx refers to any of the TMS320C2xx devices, except where device-specific information is explicitly stated.
How to Use This Manual iv For this information: Look here: Addressing modes (for addressing data memory) Chapter 6, Addressing Modes Assembly language instructions Chapter 7, Assembly Language Instructions Assembly language instructions of TMS320C1x, ’C2x, ’C2xx, and ’C5x compared Appendix B, TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison Boot loader Chapter 4, Memory and I/O Spaces Clock generator Chapter 8, On-Chip Peripherals CPU Chapter 3, Central Processing Unit Custom ROM from TI A
Notational Conventions/Information About Cautions Notational Conventions This document uses the following conventions: - Program listings and program examples are shown in a special typeface. Here is a segment of a program listing: OUTPUT LDP BLDD RET - #6 #300, 20h ;select data page 6 ;move data at address 300h to 320h In syntax descriptions, bold portions of a syntax should be entered as shown; italic portions of a syntax identify information that you specify.
Related Documentation From Texas Instruments Related Documentation From Texas Instruments This subsection describes related TI documents that can be ordered by calling the Texas Instruments Literature Response Center at (800) 477–8924. When ordering, please identify the document by its title and literature number.
Related Documentation From Texas Instruments TMS320C2xx Simulator Getting Started (literature number SPRU137) describes how to install the TMS320C2xx simulator and the C source debugger for the ’C2xx. The installation for MS-DOS, PC-DOS, SunOS, Solaris, and HP-UX systems is covered. TMS320C2xx Emulator Getting Started Guide (literature number SPRU209) tells you how to install the Windows 3.1 and Windows 95 versions of the ’C2xx emulator and C source debugger interface.
Related Articles Related Articles “A Greener World Through DSP Controllers”, Panos Papamichalis, DSP & Multimedia Technology, September 1994. “A Single-Chip Multiprocessor DSP for Image Processing—TMS320C80”, Dr. Ing. Dung Tu, Industrie Elektronik, Germany, March 1995. “Application Guide with DSP Leading-Edge Technology”, Y. Nishikori, M. Hattori, T. Fukuhara, R.Tanaka, M. Shimoda, I. Kudo, A.Yanagitani, H. Miyaguchi, et al., Electronics Engineering, November 1995.
Related Articles “Fixed or Floating? A Pointed Question in DSPs”, Jim Larimer and Daniel Chen, EDN, August 3, 1995. “Function-Focused Chipsets: Up the DSP Integration Core”, Panos Papamichalis, DSP & Multimedia Technology, March/April 1995. “GSM: Standard, Strategien und Systemchips”, Edgar Auslander, Elektronik Praxis, Germany, October 6, 1995. “High Tech Copiers to Improve Images and Reduce Paperwork”, Karl Guttag, Document Management, July/August 1995.
Trademarks Trademarks TI, 320 Hotline On-line, XDS510, XDS510PP, XDS510WS, and XDS511 are trademarks of Texas Instruments Incorporated. HP-UX is a trademark of Hewlett-Packard Company. Intel is a trademark of Intel Corporation. MS-DOS and Windows are registered trademarks of Microsoft Corporation. PAL is a registered trademark of Advanced Micro Devices, Inc. OS/2, PC, and PC-DOS are trademarks of International Business Machines Corporation. Solaris and SunOS are trademarks of Sun Microsystems, Inc.
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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Summarizes the features of the TMS320 family of products and presents typical applications. Describes the TMS320C2xx DSP and lists its key features. 1.1 1.2 1.3 2 TMS320 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.
Contents 3 Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Describes the TMS320C2xx CPU. Includes information about the central arithmetic logic unit, the accumulator, the shifters, the multiplier, and the auxiliary register arithmetic unit. Concludes with a description of the status register bits. 3.1 3.2 3.3 3.4 3.5 4 Memory and I/O Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 5 Program Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Describes the TMS320C2xx hardware and software features used in controlling program flow, including program-address generation logic and interrupts. Also describes the reset operation and power-down mode. 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 6 Program-Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 6.3 7 Assembly Language Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Describes the TMS320C2xx assembly language instructions in alphabetical order. Begins with a summary of the TMS320C2xx instructions. 7.1 7.2 7.3 8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 How To Use the Instruction Descriptions . . . . . . . . . . . . . . . . . . . .
Contents 9 Synchronous Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Describes the operation and control of the TMS320C2xx on-chip synchronous serial port. 9.1 9.2 9.3 9.4 9.5 9.6 9.7 Overview of the Synchronous Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Components and Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 10.3 10.4 10.5 Controlling and Resetting the Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.3.1 Asynchronous Serial Port Control Register (ASPCR) . . . . . . . . . . . . . . . . . . . . 10-7 10.3.2 I/O Status Register (IOSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10.3.3 Baud-Rate Divisor Register (BRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10.3.
Contents D Submitting ROM Codes to TI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 Explains the process for submitting custom program code to TI for designing masks for the on-chip ROM on a TMS320 DSP. E Design Considerations for Using XDS510 Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures Figures 1–1 2–1 2–2 3–1 3–2 3–3 3–4 3–5 3–6 3–7 3–8 3–9 3–10 3–11 4–1 4–2 4–3 4–4 4–5 4–6 4–7 4–8 4–9 4–10 4–11 4–12 4–13 4–14 4–15 4–16 4–17 5–1 5–2 5–3 5–4 xx TMS320 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Overall Block Diagram of the ’C2xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Bus Structure Block Diagram . . . . . . . . . . . . . . . . . . .
Figures 5–5 5–6 5–7 5–8 5–9 5–10 6–1 6–2 6–3 6–4 6–5 6–6 7–1 7–2 7–3 7–4 8–1 8–2 8–3 8–4 8–5 8–6 8–7 9–1 9–2 9–3 9–4 9–5 9–6 9–7 9–8 9–9 9–10 10–1 10–2 10–3 10–4 10–5 10–6 10–7 11–1 INT2/INT3 Request Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 Maskable Interrupt Operation Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 ’C2xx Interrupt Flag Register (IFR) — Data-Memory Address 0006h . . . . .
Figures 11–2 11–3 11–4 11–5 C–1 D–1 E–1 E–2 E–3 E–4 E–5 E–6 E–7 E–8 E–9 E–10 E–11 E–12 E–13 E–14 E–15 xxii ’C209 Interrupt Flag Register (IFR) — Data-Memory Address 0006h . . . . . . . . . . . . . . . 11-12 ’C209 Interrupt Mask Register (IMR) — Data-Memory Address 0004h . . . . . . . . . . . . . 11-13 ’C209 Timer Control Register (TCR) — I/O Address FFFCh . . . . . . . . . . . . . . . . . . . . . . 11-15 ’C209 Wait-State Generator Control Register (WSGR) — I/O Address FFFFh . . . . . . .
Tables Tables 1–1 1–2 2–1 2–2 3–1 3–2 4–1 4–2 4–3 4–4 4–5 4–6 4–7 4–8 5–1 5–2 5–3 5–4 5–5 5–6 5–7 6–1 6–2 6–3 7–1 7–2 7–3 7–4 7–5 7–6 7–7 7–8 8–1 8–2 8–3 8–4 Typical Applications for TMS320 DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 ’C2xx Generation Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Program and Data Memory on the TMS320C2xx Devices . . . . . . . . . . . . . . . . . . . . .
Tables 9–1 9–2 9–3 9–4 9–5 9–6 10–1 10–2 10–3 10–4 11–1 11–2 11–3 11–4 11–5 A–1 A–2 A–3 B–1 B–2 C–1 C–2 E–1 E–2 xxiv SSP Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 Run and Emulation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 Controlling Transmit Interrupt Generation by Writing to Bits FT1 and FT0 . . . . . . . . . . . . .
Examples Examples 4–1 6–1 6–2 6–3 6–4 6–5 6–6 6–7 6–8 6–9 6–10 6–11 6–12 6–13 C–1 C–2 C–3 C–4 C–5 C–6 C–7 C–8 C–9 C–10 C–11 C–12 C–13 C–14 C–15 C–16 E–1 E–2 E–3 E–4 An Interrupt Service Routine Supporting INT1 and HOLD . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 RPT Instruction Using Short-Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 ADD Instruction Using Long-Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes, Cautions, and Warnings Cautions Obtain the Proper Timing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Do Not Write to Test/Emulation Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Obtain the Proper Timing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Do Not Write to Reserved Addresses . . . . . .
Chapter 1 Introduction The TMS320C2xx (’C2xx) is one of several fixed-point generations of DSPs in the TMS320 family. The ’C2xx is source-code compatible with the TMS320C2x. Much of the code written for the ’C2x can be reassembled to run on a ’C2xx device. In addition, the ’C2xx generation is upward compatible with the ’C5x generation of DSPs. Topic Page 1.1 TMS320 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 TMS320C2xx Generation . . .
TMS320 Family 1.1 TMS320 Family The TMS320 family consists of fixed-point, floating-point, and multiprocessor digital signal processors (DSPs). TMS320 DSPs have an architecture designed specifically for real-time signal processing. The following characteristics make this family the ideal choice for a wide range of processing applications: 1.1.
TMS320 Family Figure 1–1.
TMS320 Family 1.1.2 Typical Applications for the TMS320 Family Table 1–1 lists some typical applications for the TMS320 family of DSPs. The TMS320 DSPs offer adaptable approaches to traditional signal-processing problems such as filtering and vocoding. They also support complex applications that often require multiple operations to be performed simultaneously. Table 1–1.
TMS320C2xx Generation 1.2 TMS320C2xx Generation Texas Instruments uses static CMOS integrated-circuit technology to fabricate the TMS320C2xx DSPs. The architectural design of the ’C2xx is based on that of the ’C5x. The operational flexibility and speed of the ’C2xx and ’C5x are a result of an advanced, modified Harvard architecture (which has separate buses for program and data memory), a multilevel pipeline, on-chip peripherals, on-chip memory, and a highly specialized instruction set.
Key Features of the TMS320C2xx 1.3 Key Features of the TMS320C2xx Key features on the various ’C2xx devices are: - Speed: J J J J 1-6 Source-code compatible with all ’C1x and ’C2x devices Upward compatible with the ’C5x devices Memory: J J - 20, 28.
Key Features of the TMS320C2xx - - Instruction set: J J J J J J J J - Single-cycle multiply/accumulate instructions Memory block management move instructions for better program/data Indexed-addressing capability Bit-reversed indexed-addressing capability for radix-2 FFTs On-chip peripherals: J - Single-instruction repeat operation J J Software-programmable timer Software-programmable wait-state generator for program, data, and I/O memory spaces Oscillator and phase-locked loop (PLL) to imp
Chapter 2 Architectural Overview This chapter provides an overview of the architectural structure and components of the ’C2xx. The ’C2xx DSPs use an advanced, modified Harvard architecture that maximizes processing power by maintaining separate bus structures for program memory and data memory. The three main components of the ’C2xx are the central processing unit (CPU), memory, and on-chip peripherals. Figure 2–1 shows an overall block diagram of the ’C2xx.
Architectural Overview Figure 2–1.
’C2xx Bus Structure 2.1 ’C2xx Bus Structure Figure 2–2 shows a block diagram of the ’C2xx bus structure. The ’C2xx internal architecture is built around six 16-bit buses: - PAB. The program address bus provides addresses for both reads from and writes to program memory. DRAB. The data-read address bus provides addresses for reads from data memory. DWAB. The data-write address bus provides addresses for writes to data memory. PRDB.
’C2xx Bus Structure Figure 2–2.
Central Processing Unit 2.2 Central Processing Unit The CPU is the same on all the ’C2xx devices. The ’C2xx CPU contains: 2.2.
Central Processing Unit 2.2.3 Multiplier The on-chip multiplier performs 16-bit × 16-bit 2s-complement multiplication with a 32-bit result. In conjunction with the multiplier, the ’C2xx uses the 16-bit temporary register (TREG) and the 32-bit product register (PREG). The TREG always supplies one of the values to be multiplied. The PREG receives the result of each multiplication.
Memory and I/O Spaces 2.3 Memory and I/O Spaces The ’C2xx memory is organized into four individually selectable spaces: program, local data, global data, and I/O. These spaces form an address range of 224K words. All ’C2xx devices include 288 words of dual-access RAM (DARAM) for data memory and 256 words of data/program DARAM. Depending on the device, it may also have data/program single-access RAM (SARAM) and read-only memory (ROM) or flash memory.
Memory and I/O Spaces CPU reads data on the third cycle and writes data on the fourth cycle. However, DARAM allows the CPU to write and read in one cycle; the CPU writes to DARAM on the master phase of the cycle and reads from DARAM on the slave phase. For example, suppose two instructions, A and B, store the accumulator value to DARAM and load the accumulator with a new value from DARAM.
Memory and I/O Spaces 2.3.4 Flash Memory Some of the ’C2xx devices feature on-chip blocks of flash memory, which is electronically erasable and programmable, and non-volatile. Each block of flash memory will have a set of control registers that allow for erasing, programming, and testing of that block. The flash memory blocks can be selected during reset by driving the MP/MC pin low. If the flash memory is not selected, the device starts its execution from off-chip memory.
Program Program Control Control 2.4 Program Control Several features provide program control: - The program controller of the CPU decodes instructions, manages the pipeline, stores the status of operations, and decodes conditional operations. Elements involved in program control are the program counter, the status registers, the stack, and the address-generation logic.
On-Chip Peripherals 2.5 On-Chip Peripherals All the ’C2xx devices have the same CPU, but different on-chip peripherals are connected to their CPUs. The on-chip peripherals featured on the ’C2xx devices are: 2.5.
On-Chip Peripherals 2.5.5 General-Purpose I/O Pins The ’C2xx has pins that provide general-purpose input or output signals. All ’C2xx devices have a general-purpose input pin, BIO, and a general-purpose output pin, XF. Except for the ’C209, the ’C2xx devices also have pins IO0, IO1, IO2, and IO3, which are connected to corresponding bits (IO0–IO3) mapped into the on-chip I/O space. These bits can be individually configured as inputs or outputs.
Scanning-Logic Circuitry 2.6 Scanning-Logic Circuitry The ’C2xx has JTAG scanning-logic circuitry that is compatible with IEEE Standard 1149.1. This circuitry is used for emulation and testing purposes only. The serial scan path is used to test pin-to-pin continuity as well as to perform operational tests on the on-chip peripherals. The internal scanning logic provides access to all of the on-chip resources. Thus, the serial-scan pins and the emulation pins on ’C2xx devices allow on-board emulation.
Chapter 3 Central Processing Unit This chapter describes the main components of the central processing unit (CPU). First, this chapter describes three fundamental sections of the CPU (see Figure 3–1): - Input scaling section Multiplication section Central arithmetic logic section The chapter then describes the auxiliary register arithmetic unit (ARAU), which performs arithmetic operations independently of the central arithmetic logic section.
Central Processing Unit Figure 3–1.
Input Scaling Section 3.1 Input Scaling Section A 32-bit input data-scaling shifter (input shifter) aligns a 16-bit value coming from memory to the 32-bit CALU. This data alignment is necessary for datascaling arithmetic as well as aligning masks for logical operations. The input shifter operates as part of the data path between program or data space and the CALU and, thus, requires no cycle overhead. Described directly below are the input, the output, and the shift count of the input shifter.
Input Scaling Section Shift count. The shifter can left-shift a 16-bit value by 0 to 16 bits. The size of the shift (or the shift count) is obtained from one of two sources: - A constant embedded in the instruction word. Putting the shift count in the instruction word allows you to use specific data-scaling or alignment operations customized for your program code. The four LSBs of the temporary register (TREG).
Multiplication Section 3.2 Multiplication Section The ’C2xx uses a 16-bit × 16-bit hardware multiplier that can produce a signed or unsigned 32-bit product in a single machine cycle.
Multiplication Section Inputs. The multiplier accepts two 16-bit inputs: - One input is always from the 16-bit temporary register (TREG). The TREG is loaded before the multiplication with a data-value from the data read bus (DRDB). The other input is one of the following: J J A data-memory value from the data read bus (DRDB). A program memory value from the program read bus (PRDB). Output. After the two 16-bit inputs are multiplied, the 32-bit result is stored in the product register (PREG).
Multiplication Section ÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Table 3–1.
Central Arithmetic Logic Section 3.3 Central Arithmetic Logic Section Figure 3–6 shows the main components of the central arithmetic logic section, which are: - The central arithmetic logic unit (CALU), which implements a wide range of arithmetic and logic functions. The 32-bit accumulator (ACC), which receives the output of the CALU and is capable of performing bit shifts on its contents with the help of the carry bit (C). Figure 3–6 shows the accumulator’s high word (ACCH) and low word (ACCL).
Central Arithmetic Logic Section 3.3.1 Central Arithmetic Logic Unit (CALU) The central arithmetic logic unit (CALU), implements a wide range of arithmetic and logic functions, most of which execute in a single clock cycle. These functions can be grouped into four categories: - 16-bit addition 16-bit subtraction Boolean logic operations Bit testing, shifting, and rotating. Because the CALU can perform Boolean operations, you can perform bit manipulation.
Central Arithmetic Logic Section Status bits. Four status bits are associated with the accumulator: - Carry bit (C). C (bit 9 of status register ST1) is affected during: J Additions to and subtractions from the accumulator: C=0 When the result of a subtraction generates a borrow. When the result of an addition does not generate a carry. (Exception: When the ADD instruction is used with a shift of 16 and no carry is generated, the ADD instruction has no affect on C.
Central Arithmetic Logic Section 3.3.3 Output Data-Scaling Shifter The output data-scaling shifter (output shifter) has a 32-bit input connected to the 32-bit output of the accumulator and a 16-bit output connected to the data bus. The shifter copies all 32-bits of the accumulator and then performs a left shift on its content; it can be shifted from zero to seven bits, as specified in the corresponding store instruction.
Auxiliary Register Arithmetic Unit (ARAU) 3.4 Auxiliary Register Arithmetic Unit (ARAU) The CPU also contains the auxiliary register arithmetic unit (ARAU), an arithmetic unit independent of the central arithmetic logic unit (CALU). The main function of the ARAU is to perform arithmetic operations on eight auxiliary registers (AR7 through AR0) in parallel with operations occurring in the CALU. Figure 3–9 shows the ARAU and related logic. Figure 3–9.
Auxiliary Register Arithmetic Unit (ARAU) The eight auxiliary registers (AR7–AR0) provide flexible and powerful indirect addressing. Any location in the 64K data memory space can be accessed using a 16-bit address contained in an auxiliary register. For the details of indirect addressing, see Section 6.3 on page 6-9. To select a specific auxiliary register, load the 3-bit auxiliary register pointer (ARP) of status register ST0 with a value from 0 through 7.
Auxiliary Register Arithmetic Unit (ARAU) execute phase of the pipeline. For information on the operation of the pipeline, see Section 5.2 on page 5-7. In addition to using the auxiliary registers to reference data-memory addresses, you can use them for other purposes. For example, you can: - 3-14 Use the auxiliary registers to support conditional branches, calls, and returns by using the CMPR instruction.
Status Registers ST0 and ST1 3.5 Status Registers ST0 and ST1 The ’C2xx has two status registers, ST0 and ST1, which contain status and control bits. These registers can be stored into and loaded from data memory, thus allowing the status of the machine to be saved and restored for subroutines.
Status Registers ST0 and ST1 Table 3–2. Bit Fields of Status Registers ST0 and ST1 Name Description ARB Auxiliary register pointer buffer. Whenever the auxiliary register pointer (ARP) is loaded, the previous ARP value is copied to the ARB, except during an LST (load status register) instruction. When the ARB is loaded by an LST instruction, the same value is also copied to the ARP. ARP Auxiliary register pointer. This 3-bit field selects which auxiliary register (AR) to use in indirect addressing.
Status Registers ST0 and ST1 Table 3–2. Bit Fields of Status Registers ST0 and ST1 (Continued) Name Description OVM Overflow mode bit. OVM determines how overflows in the CALU are handled. The SETC and CLRC instructions set and clear this bit, respectively. An LST instruction can also be used to modify OVM. PM SXM OVM = 0 Results overflow normally in the accumulator. OVM = 1 The accumulator is set to either its most positive or negative value upon encountering an overflow. (See subsection 3.3.
Chapter 4 Memory and I/O Spaces This chapter describes the ’C2xx memory configuration options and the address maps of the individual ’C2xx devices. It also illustrates typical ways of interfacing the ’C2xx with external memory and external input/output (I/O) devices.
Overview of the Memory and I/O Spaces 4.1 Overview of the Memory and I/O Spaces The ’C2xx address map is organized into four individually selectable spaces: - Program memory (64K words) contains the instructions to be executed, as well as data used during program execution. Local data memory (64K words) holds data used by the instructions. Global data memory (32K words) shares data with other processors or serves as additional data space.
Overview of the Memory and I/O Spaces 4.1.1 Pins for Interfacing to External Memory and I/O Spaces The pins for interfacing to external memory and I/O space, described in Table 4–1, are of four main types: - External buses. Sixteen signals (A15–A0) are available for passing an address from the ’C2xx to another device. Sixteen signals (D15–D0) are available for transferring a data value between the ’C2xx and another device. Select signals.
Overview of the Memory and I/O Spaces Table 4–1. Pins for Interfacing With External Memory and I/O Spaces (Continued) Read/write signals Request/control signals 4-4 Pin(s) Description R/W Read/write pin. This pin indicates the direction of transfer between the ’C2xx and external program, data, or I/O space. RD Read select pin. The ’C2xx asserts RD to request a read from external program, data, or I/O space. WE Write enable pin.
Program Memory 4.2 Program Memory Program-memory space holds the code for applications; it can also hold table information and constant operands. The program-memory space addresses up to 64K 16-bit words. Every ’C2xx device contains a DARAM block B0 that can be configured as program memory or data memory. Other on-chip program memory may be SARAM and ROM or flash memory. For information on configuring on-chip program-memory blocks, see Section 4.8. 4.2.
Program Memory Figure 4–1.
Local Data Memory 4.3 Local Data Memory The local data-memory space addresses up to 64K 16-bit words. Every ’C2xx device has three on-chip DARAM blocks: B0, B1, and B2. Block B0 has 256 words that are configurable as either data locations or program locations. Blocks B1 (256 words) and B2 (32 words) have a total of 288 words that are available for data memory only. Some ’C2xx devices, in addition to the three DARAM blocks, have an on-chip SARAM block that can be used for program and/or data memory.
Local Data Memory 4.3.1 Data Page 0 Address Map Table 4–2 shows the address map of data page 0 (addresses 0000h–007Fh). Note the following: - Three memory-mapped registers can be accessed with zero wait states: J J J Interrupt mask register (IMR) Global memory allocation register (GREG) Interrupt flag register (IFR) The test/emulation reserved area is used by the test and emulation systems for special information transfers.
Local Data Memory 4.3.2 Interfacing With External Local Data Memory While the ’C2xx is accessing the on-chip local data-memory blocks, the external memory signals DS and STRB are in high impedance. The external buses are active only when the ’C2xx is accessing locations within the address ranges mapped to external memory. An active DS signal indicates that the external buses are being used for data memory.
Local Data Memory Figure 4–3.
Global Data Memory 4.4 Global Data Memory Addresses in the upper 32K words (8000h–FFFFh) of local data memory can be used for global data memory. The global memory allocation register (GREG) determines the size of the global data-memory space, which is between 256 and 32K words. The GREG is connected to the eight LSBs of the internal data bus and is memory-mapped to data-memory location 0005h.
Global Data Memory As an example of configuring global memory, suppose you want to designate 8K addresses as global addresses. You would write the 8-bit value 111000002 to the eight LSBs of the GREG (see Figure 4–4). This would designate addresses E000h–FFFFh of data memory as global data addresses (see Figure 4–5). Figure 4–4. GREG Register Set to Configure 8K for Global Data Memory 8 MSBs X X X X X 8 LSBs X X X (Don’t cares) 1 1 1 0 0 0 0 0 Set for 8K of global data memory Figure 4–5.
Global Data Memory toggled between local memory and global memory. For example, in the system of Figure 4–6, when GREG = XXXXXXXX000000002 (no global memory), the local data RAM is fully accessible; when GREG = XXXXXXXX100000002 (all global memory), the local data RAM is not accessible. Figure 4–6.
Boot Loader 4.5 Boot Loader This section applies to ’C2xx devices that have an on-chip boot loader. The boot loader is used for booting software from an 8-bit external ROM to a 16-bit external RAM at reset (see Figure 4–7). The source for your program is an external ROM located in external global data memory. The destination for the boot loaded program is RAM in program space.
Boot Loader 4.5.2 Connecting the EPROM to the Processor To map the EPROM into the global data space at address 8000h, make the following connections between the processor and the EPROM (refer to Figure 4–8): - Connect the address lines of the processor and the EPROM (see lines A14–A0 in the figure). Connect the data lines of the processor and the EPROM (see lines D7–D0 in the figure). Connect the processor’s RD pin to the EPROM’s output enable pin (OE in the figure).
Boot Loader 4.5.3 Programming the EPROM Texas Instruments fixed-point development tools provide the utilities to generate the boot ROM code. (For an introduction to the procedure for generating boot loader code, see Appendix C, Program Examples.) However, should you need to do the programming, use the following procedure. Store the following to the EPROM: - Destination address.
Boot Loader Figure 4–9 shows how to store a 16-bit program into the 8-bit EPROM. A subscript h (for example, on Word1h ) indicates the high-byte and a subscript l (for example, on Word1l ) indicates the low byte. Figure 4–9. Storing the Program in the EPROM 16-Bit Program 15 4.5.4 8-Bit EPROM 8 7 0 Address 7 0 Word1h Word1l 8000h Destinationh Word2h Word2l 8001h Destinationl •.
Boot Loader 4.5.5 Boot Loader Execution Once the EPROM has been programmed and installed, and the boot loader has been enabled, the processor automatically boots the program from EPROM at startup. If you need to reboot the processor during operation, bring the RS pin low to cause a hardware reset. When the processor executes the boot loader, the program first enables the full 32K words of global data memory by setting the eight LSBs of the GREG register to 80h.
Boot Loader Figure 4–10. Program Code Transferred From 8-Bit EPROM to 16-Bit RAM 8-Bit EPROM Address 7 16-Bit RAM 0 Address 15 8 7 0 8000h Destinationh = 00h 0000h Word1h Word1l 8001h Destinationl = 00h • Word2h Word2l 8002h Length Nh • •.
Boot Loader Figure 4–11.
Boot Loader 4.5.6 Boot Loader Program ********************************************************************************* * TMS320C2xx Boot Loader Program * * * * This code sets up and executes boot loader code that loads program * * code from location 8000h in external global data space and transfers it * * to the destination address specified by the first word read from locations * * 8000h and 8001h. * ********************************************************************************* .length 60 GREG .
Boot Loader * * Transfer code * LOOP LACC SACL LACL AND OR SACL LACL TBLW ADD SACL BANZ SPLK INTR *+,8 HBYTE *+,AR0 #0FFH HBYTE CODEWORD DEST CODEWORD #1 DEST LOOP,AR1 #0,GREG 0 ; ; ; ; ; ; ; ; ; ; ; ; ; Load ACC with high byte of code shifted by 8 bits Store high byte Load ACC with low byte of code Mask off upper 24 bits OR ACC with high byte to form 16-bit code word Store code word Load destination address Transfer code to destination address Add 1 to destination address Save new address Determine if
I/O Space 4.6 I/O Space The ’C2xx supports an I/O address range of 64K 16-bit words. Figure 4–12 shows the ’C2xx I/O address map. Figure 4–12.
I/O Space The map has three main sections of addresses: - Addresses 0000h–FEFFh allow access to off-chip peripherals typically used in DSP applications, such as digital-to-analog and analog-to-digital converters. Addresses FF00h–FF0Fh are mapped to on-chip I/O space. These addresses are reserved for test purposes and should not be used. Addresses FF10h–FFFFh are also mapped to on-chip I/O space. These addresses are used for other reserved space and for the on-chip I/Omapped registers.
I/O Space 4.6.1 Accessing I/O Space All I/O words (external I/O ports and on-chip I/O registers) are accessed with the IN and OUT instructions. Accesses to external parallel I/O ports are multiplexed over the same address and data buses for program and data-memory accesses. These accesses are distinguished from external program and datamemory accesses by IS going low.
I/O Space ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Figure 4–13.
Direct Memory Access Using the HOLD Operation 4.7 Direct Memory Access Using the HOLD Operation The ’C2xx HOLD operation allows direct-memory access to external program, data, and I/O spaces. The process is controlled by two signals: - HOLD. An external device can drive the HOLD/INT1 pin low to request control over the external buses. If the HOLD/INT1 interrupt line is enabled, this triggers an interrupt. HOLDA.
Direct Memory Access Using the HOLD Operation Example 4–1. An Interrupt Service Routine Supporting INT1 and HOLD ICR ICRSHDW * .mmregs .set 0FFECh .set 060h Interrupt vectors reset Int1h main: wait: B B .space SPLK CLRC B ;Include c2xx memory–mapped registers. ;Define interrupt control register in I/O space. ;Define ICRSHDW in scratch pad location. * main int1_hold 40*16 #0001h,imr INTM wait ;0 – reset , Branch to main program on reset. ;1 – external interrupt 1 or HOLD.
Direct Memory Access Using the HOLD Operation Here are three valid methods for exiting the IDLE state, thus deasserting HOLDA and restoring the buses to normal operation: - Cause a rising edge on the HOLD/INT1 pin when MODE = 0. Assert system reset at the reset pin. Assert the nonmaskable interrupt NMI at the NMI pin. If reset or NMI occurs while HOLDA is asserted, the CPU will deassert HOLDA regardless of the level on the HOLD/INT1 pin.
Direct Direct Memory Memory Access Access Using Using the the HOLD HOLD Operation Operation Figure 4–15.
Device-Specific Information 4.8 Device-Specific Information For ’C2xx devices other than the ’C209, this section mentions the presence or absence of the boot loader and HOLD features, shows address maps, and explains the contents and configuration of the program-memory and datamemory maps. For details about the memory and I/O spaces of the ’C209, see Section 11.2 on page 11-5. 4.8.
Device-Specific Information Figure 4–16.
Device-Specific Information DARAM blocks B1 and B2 are fixed, but DARAM block B0 may be mapped to program space or data space, depending on the value of the CNF bit (bit 12 of status register ST1): - CNF = 0. B0 is mapped to data space and is accessible at data addresses 0200h–02FFh. Note that the addressable external program memory increases by 512 words. CNF = 1. B0 is mapped to program space and is accessible at program addresses FF00h–FFFFh. At reset, CNF = 0.
Device-Specific Information Table 4–6. ’C203 Data-Memory Configuration Options CNF DARAM B0 (hex) DARAM B1 (hex) DARAM B2 (hex) External (hex) Reserved (hex) 0 0200–02FF 0300–03FF 0060–007F 0800–FFFF 0000–005F 0080–01FF 0400–07FF 1 – 0300–03FF 0060–007F 0800–FFFF 0000–005F 0080–02FF 0400–07FF 4.8.2 TMS320C204 Address Maps and Memory Configuration The ’C204 does not have an on-chip boot loader, but it does support the ’C2xx HOLD operation. Figure 4–16 shows the ’C204 address map.
Device-Specific Information Figure 4–17.
Device-Specific Information You select or deselect the ROM by changing the level on the MP/MC pin at reset: - MP/MC = 0 at reset. The device is configured as a microcomputer. The on-chip ROM is enabled and is accessible at addresses 0000h–0FFFh. The device fetches the reset vector from on-chip ROM. MP/MC = 1 at reset. The device is configured as a microprocessor, and addresses 0000h–0FFFh are used to access external memory. The device fetches the reset vector from external memory.
Device-Specific Information Table 4–7. ’C204 Program-Memory Configuration Options MP/MC CNF ROM (hex) DARAM B0 (hex) External (hex) Reserved (hex) 0 0 0000–0FFF – 1000–FFFF – 0 1 0000–0FFF FF00–FFFF 1000–FDFF FE00–FEFF 1 0 – – 0000–FFFF – 1 1 – FF00–FFFF 0000–FDFF FE00–FEFF Table 4–8.
Chapter 5 Program Control This chapter discusses the processes and features involved in controlling the flow of a program on the ’C2xx. Program control involves controlling the order in which one or more blocks of instructions are executed. Normally, the flow of a program is sequential: the ’C2xx executes instructions at consecutive program-memory addresses. At times, a program must branch to a nonsequential address and then execute instructions sequentially at that new location.
Program-Address Generation 5.1 Program-Address Generation Program flow requires the processor to generate the next program address (sequential or nonsequential) while executing the current instruction. Program-address generation is illustrated in Figure 5–1 and summarized in Table 5–1. Figure 5–1.
Program-Address Generation ÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Table 5–1.
Program-Address Generation The ’C2xx can load the PC in a number of ways, to accommodate sequential and nonsequential program flow. Table 5–2 shows what is loaded to the PC according to the code operation performed.
Program-Address Generation - PSHD and POPD. These instructions allow you to build a stack in data memory for the nesting of subroutines or interrupts beyond eight levels. The PSHD instruction pushes a data-memory value onto the top of the stack. The POPD instruction pops a value from the top of the stack to data memory.
Program-Address Generation Figure 5–3. A Pop Operation Before Instruction Accumulator or memory location Stack 5.1.3 82h After Instruction Accumulator or memory location 45h 45h 16h 16h 7h 7h Stack 33h 33h 42h 42h 56h 56h 37h 37h 61h 61h 61h Micro Stack (MSTACK) The program-address generation logic uses the 16-bit-wide, 1-level-deep MSTACK to store a return address before executing certain instructions.
Pipeline Operation 5.2 Pipeline Operation Instruction pipelining consists of a sequence of bus operations that occur during the execution of an instruction. The ’C2xx pipeline has four independent stages: instruction-fetch, instruction-decode, operand-fetch, and instructionexecute. Because the four stages are independent, these operations can overlap. During any given cycle, one to four different instructions can be active, each at a different stage of completion.
Branches, Calls, and Returns 5.3 Branches, Calls, and Returns Branches, calls, and returns break the sequential flow of instructions by transferring control to another location in program memory. A branch only transfers control to the new location. A call also saves the return address (the address of the instruction following the call) to the top of the hardware stack.
Branches, Calls, and Returns By the time the unconditional call instruction reaches the execute phase of the pipeline, the next two instruction words have already been fetched. These two instruction words are flushed from the pipeline so that they are not executed, the return address is stored to the stack, and then execution continues at the beginning of the called function. The unconditional call instructions are CALL and CALA (call subroutine at location specified by accumulator). 5.3.
Conditional Branches, Calls, and Returns 5.4 Conditional Branches, Calls, and Returns The ’C2xx provides branch, call, and return instructions that will execute only if one or more conditions are met. You specify the conditions as operands of the conditional instruction. Table 5–3 lists the conditions that you can use with these instructions and their corresponding operand symbols. Table 5–3.
Conditional Branches, Calls, and Returns - Group 2. You can select up to three conditions. Each of these conditions must be from a different category (A, B, or C); you cannot have two conditions from the same category. For example, you can test TC, C, and BIO at the same time, but you cannot test C and NC at the same time. Table 5–4. Groupings of Conditions Group 1 Group 2 Category A Category B Category A Category B Category C EQ OV TC C BIO NEQ NOV NTC NC LT LEQ GT GEQ 5.4.
Conditional Branches, Calls, and Returns The conditional branch instructions are BCND (branch conditionally) and BANZ (branch if currently selected auxiliary register is not equal to 0). The BANZ instruction is useful for implementing loops. 5.4.4 Conditional Calls The conditional call (CC) instruction is executed only when the specified condition or conditions are met (see Table 5–3 on page 5-10). This allows your program to choose among multiple subroutines based on the data being processed.
Conditional Branches, Calls, and Returns RETC, like RET, is a single-word instruction. However, because of the potential PC discontinuity, it operates with the same effective execution time as the conditional branch (BCND) and the conditional call (CC). By the time the conditions of the conditional return instruction have been tested, the two instruction words following the return instruction have already been fetched in the pipeline.
Repeating a Single Instruction 5.5 Repeating a Single Instruction The ’C2xx repeat (RPT) instruction allows the execution of a single instruction N + 1 times, where N is specified as an operand of the RPT instruction. When RPT is executed, the repeat counter (RPTC) is loaded with N. RPTC is then decremented every time the repeated instruction is executed, until RPTC equals zero.
Interrupts 5.6 Interrupts Interrupts are hardware- or software-driven signals that cause the ’C2xx to suspend its current program sequence and execute a subroutine. Typically, interrupts are generated by hardware devices that need to give data to or take data from the ’C2xx (for example, A/D and D/A converters and other processors). Interrupts can also signal that a particular event has taken place (for example, a timer has finished counting).
Interrupts 3) Execute the interrupt service routine. Once the interrupt is acknowledged, the ’C2xx branches to its corresponding subroutine called an interrupt service routine (ISR). The ’C2xx follows the branch instruction you place at a predetermined address (the vector location) and executes the ISR you have written. 5.6.2 Interrupt Table For ’C2xx devices other than the ’C209, Table 5–5 lists the interrupts available and shows their vector locations.
Interrupts ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ
Interrupts 5.6.3 Maskable Interrupts When a maskable interrupt is successfully requested by a hardware device or by an external pin, the corresponding flag or flags are activated. These flags are activated whether or not the interrupt is later acknowledged by the processor. Two registers on the ’C2xx contain flag bits: - Interrupt flag register (IFR), a 16-bit, memory-mapped register located at address 0006h in data-memory space.The IFR is explained in detail in subsection 5.6.
Interrupts After an interrupt request is received by the CPU, the CPU must decide whether to acknowledge the request. Maskable hardware interrupts are acknowledged only after certain conditions are met: - Priority is highest. When more than one hardware interrupt is requested at the same time, the ’C2xx services them according to a set priority ranking in which 1 indicates the highest priority. For the priorities of the hardware interrupts, see subsection 5.6.2 (on page 5-16). IMR mask bit is 1.
Interrupts Figure 5–6 summarizes how maskable interrupts are handled by the CPU. Figure 5–6. Maskable Interrupt Operation Flow Chart Interrupt request sent to CPU Corresponding IFR flag bit set No Interrupts enabled (INTM bit = 0) ? Yes No Interrupt unmasked? Yes Interrupt acknowledged INTM bit set to 1 PC saved on stack Interrupt service routine run Return instruction restores PC Program continues 5.6.
Interrupts 1 to the corresponding IFR bit. All pending interrupts can be cleared by writing the current contents of the IFR back into the IFR. Acknowledgement of a hardware request also clears the corresponding IFR bit. A device reset clears all IFR bits. Notes: 1) When an interrupt is requested by an INTR instruction, if the corresponding IFR bit is set, the CPU will not clear it automatically.
Interrupts Bit 3 Bit 2 Bit 1 Bit 0 RINT — Receive interrupt flag. Bit 3 is tied to the receive interrupt for the synchronous serial port. To avoid double interrupts, write a 1 to this bit in the interrupt service routine. RINT = 0 Interrupt RINT is not pending. RINT = 1 Interrupt RINT is pending. TINT — Timer interrupt flag. Bit 2 is tied to the timer interrupt, TINT. TINT = 0 Interrupt TINT is not pending. TINT = 1 Interrupt TINT is pending. INT2/INT3 — Interrupt 2/Interrupt 3 flag.
Interrupts For ’C2xx devices other than the ’C209, Figure 5–8 shows the IMR. Descriptions of the bits follow the figure. For a description of the ’C209 IMR, see subsection 11.3.1, ’C209 Interrupt Registers, on page 11-11. Figure 5–8.
Interrupts Bit 0 HOLD/INT1 — HOLD/Interrupt 1 mask. This bit masks or unmasks interrupts requested at the HOLD/INT1 pin. HOLD/INT1 = 0 HOLD/INT1 is masked. HOLD/INT1 = 1 HOLD/INT1 is unmasked. 5.6.6 Interrupt Control Register (ICR) The 16-bit interrupt control register (ICR), located at address FFECh in I/O space, controls the function of the HOLD/INT1 pin and individually controls the interrupts INT2 and INT3.
Interrupts to mask INT3 (prevent the setting of flags FINT3 and INT2/INT3) write a 0 to MINT3. If INT2/INT3 is not set, the CPU has not received and will not acknowledge the interrupt request. When INT2/INT3 is set, one or both of the interrupts is pending. To differentiate the occurrences of the two interrupts, your interrupt service routine can test FINT2 and FINT3 and then branch to the appropriate subroutine.
Interrupts Figure 5–9 shows the ICR, and bit descriptions follow the figure. Figure 5–9. ’C2xx Interrupt Control Register (ICR) — I/O-Space Address FFECh ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ 15 Note: 5 4 3 2 1 0 Reserved MODE FINT3 FINT2 MINT3 MINT2 0 R/W–0 R/W1C–0 R/W1C–0 R/W–0 R/W–0 0 = Always read as zeros; R = Read access; W = Write access; W1C = Write 1 to this bit to clear it to 0; value following dash (–) is value after reset. Bits 15–5 Reserved.
Interrupts Bit 0 5.6.7 MINT2 — Interrupt 2 mask. This bit masks the external interrupt INT2 or, in conjunction with the INT2/INT3 bit of the IMR, unmasks INT2. MINT2 = 0 INT2 is masked. Neither FINT2 nor bit 1 of the IFR (INT2/INT3) is set by a request on the INT2 pin. MINT2 = 1 INT3 is unmasked. Flag bits FINT2 and INT2/INT3 are both set by a request on the INT2 pin. Nonmaskable Interrupts Hardware nonmaskable interrupts can be requested through two pins: - - RS (reset).
Interrupts Note: The INTR instruction does not affect IFR flags. When you use the INTR instruction to initiate an interrupt that has an associated flag bit in the IFR, the instruction neither sets nor clears the flag bit. No software write operation can set the IFR flag bits; only the appropriate hardware requests can. If a hardware request has set the flag for an interrupt and then the INTR instruction is used to initiate that interrupt, the INTR instruction will not clear the flag. - - NMI.
Interrupts Figure 5–10. Nonmaskable Interrupt Operation Flow Chart Interrupt request sent to CPU Interrupt acknowledged TRAP instruction? No INTM bit set to 1 Yes PC saved on stack Interrupt service routine run Return instruction restores PC Program continues 5.6.8 Interrupt Service Routines (ISRs) After an interrupt has been requested and acknowledged, the CPU follows an interrupt vector to the ISR. The ISR is the program code that actually performs the tasks requested by the interrupt.
Interrupts Managing ISRs within ISRs The ’C2xx hardware stack allows you to have ISRs within ISRs. When considering nesting ISRs like this, keep the following in mind: - - If you want the ISR be interrupted by a maskable interrupt, the ISR must unmask the interrupt by setting the appropriate IMR bit (and ICR bit, if applicable) and executing the enable-interrupts instruction (CLRC INTM). The hardware stack is limited to eight levels.
Interrupts For an external, maskable hardware interrupt, a minimum latency of eight cycles is required to synchronize the interrupt externally, recognize the interrupt, and branch to the interrupt vector location. On the ninth cycle, the interrupt vector is fetched. For a software interrupt, the minimum latency consists of four cycles needed to branch to the interrupt vector location. Latency for pipeline protection Multicycle instructions add additional cycles to empty the pipeline.
Interrupts before the return, the new return address would be added to the hardware stack, even if the stack were already full. To allow the CPU to complete the return, interrupts are also blocked after a RET instruction until at least one instruction at the return address is executed.
Reset Operation 5.7 Reset Operation Reset (RS) is a nonmaskable external interrupt that can be used at any time to put the ’C2xx into a known state. Reset is the highest priority interrupt; no other interrupt takes precedence over reset. Reset is typically applied after power up when the machine is in an unknown state. Because the reset signal aborts memory operations and initializes status bits, the system should be reinitialized after each reset.
Reset Operation - Peripherals: J J The timer count is set to its maximum value (FFFFh), the timer dividedown value is set to 0, and the timer starts counting down. The synchronous serial port is reset: H H H H J J H H H H The port emulation mode is set to immediate stop. Error and status flags are reset. Receive interrupts are set to occur when the receive buffer is not empty. Transmit interrupts are set to occur when the transmit buffer can accept one or more words.
Reset Operation Table 5–6. Reset Values of On-Chip Registers Mapped to Data Space Name Data-Memory Address Reset Value Description IMR 0004h 0000h Interrupt mask register GREG 0005h 0000h Interrupt control register IFR 0006h 0000h Synchronous data transmit and receive register Table 5–7.
Power-Down Mode 5.8 Power-Down Mode The ’C2xx has a power-down mode that allows the ’C2xx core to enter a dormant state and use less power than during normal operation. Executing an IDLE instruction initiates power-down mode. When the IDLE instruction executes, the program counter is incremented once, and then all CPU activities are halted. While the ’C2xx is in power-down mode, all of its internal contents are maintained. The content of all on-chip RAM remains unchanged.
Power-Down Mode 5.8.2 Termination of Power-Down During a HOLD Operation One of the necessary steps in the HOLD operation is the execution of an IDLE instruction (see Section 4.7, Direct Memory Access Using The HOLD Operation, on page 4-27) . There are unique characteristics of the HOLD operation that affect how the IDLE state can be exited. Before performing a HOLD operation, your program must write a 0 to the MODE bit (bit 4 of the interrupt control register, ICR).
Chapter 6 Addressing Modes This chapter explains the three basic memory addressing modes used by the ’C2xx instruction set. The three modes are: - Immediate addressing mode Direct addressing mode Indirect addressing mode In immediate addressing, a constant to be manipulated by the instruction is supplied directly as an operand of that instruction. Two types of immediate addressing are available—short and long.
Immediate Addressing Mode 6.1 Immediate Addressing Mode In immediate addressing, the instruction word contains a constant to be manipulated by the instruction. The ’C2xx supports two types of immediate addressing: - Short-immediate addressing. Instructions that use short-immediate addressing take an 8-bit, 9-bit, or 13-bit constant as an operand. Short-immediate instructions require a single instruction word, with the constant embedded in that word. - 6.1.1 Long-immediate addressing.
Immediate Addressing Mode Figure 6–2.
Direct Addressing Mode 6.2 Direct Addressing Mode In the direct addressing mode, data memory is addressed in blocks of 128 words called data pages. The entire 64K of data memory consists of 512 data pages labeled 0 through 511, as shown in Figure 6–3. The current data page is determined by the value in the 9-bit data page pointer (DP) in status register ST0. For example, if the DP value is 0000000002, the current data page is 0. If the DP value is 0000000102, the current data page is 2. Figure 6–3.
Direct Addressing Mode Figure 6–4. Instruction Register (IR) Contents in Direct Addressing Mode 15 14 13 12 11 10 9 8 7 6 5 4 0 8 MSBs 3 2 1 0 7 LSBs 8 MSBs Bits 15 through 8 indicate the instruction type (for example, ADD) and also contain any information regarding a shift of the data value to be accessed by the instruction. 0 Direct/indirect indicator. Bit 7 contains a 0 to define the addressing mode as direct.
Direct Addressing Mode 6.2.1 Using Direct Addressing Mode When you use direct addressing mode, the processor uses the DP to find the data page and uses the seven LSBs of the instruction register to find a particular address on that page. Always do the following: 1) Set the data page. Load the appropriate value (from 0 to 511) into the DP. The DP register can be loaded by the LDP instruction or by any instruction that can load a value to ST0.
Direct Addressing Mode Example 6–3. Using Direct Addressing with ADD (Shift of 0 to 15) LDP #4 ;Set data page to 4 (addresses 0200h–027Fh). ADD 9h,5 ;The contents of data address 0209h are ;left–shifted 5 bits and added to the ;contents of the accumulator.
Direct Addressing Mode In Example 6–5, the ADDC instruction references a data memory address that is generated as shown following the program code. Note that if an instruction does not perform shifts, like the ADDC instruction does not, all eight MSBs of the instruction contain the opcode for the instruction type. Example 6–5. Using Direct Addressing with ADDC LDP #500 ;Set data page to 500 (addresses FA00h–FA7Fh).
Indirect Addressing Mode 6.3 Indirect Addressing Mode Eight auxiliary registers (AR0–AR7) provide flexible and powerful indirect addressing. Any location in the 64K data memory space can be accessed using a 16-bit address contained in an auxiliary register. 6.3.1 Current Auxiliary Register To select a specific auxiliary register, load the 3-bit auxiliary register pointer (ARP) of status register ST0 with a value from 0 to 7.
Indirect Addressing Mode ister as the data memory address and then increments or decrements the content of the current auxiliary register by the index amount. - Increment or decrement by an index amount using reverse carry. The value in AR0 is the index amount. After the instruction uses the content of the current auxiliary register as the data-memory address, that content is incremented or decremented by the index amount.
Indirect Addressing Mode Table 6–1. Indirect Addressing Operands (Continued) Option Operand Example Increment by index amount, adding with reverse carry *BR0+ LT *BR0+ loads the temporary register (TREG) with the content of the data memory address referenced by the current AR and then adds the content of AR0 to the content of the current AR, adding with reverse carry propagation.
Indirect Addressing Mode Example 6–6. Selecting a New Current Auxiliary Register MAR*,AR1 ;Load the ARP with 1 to make AR1 the ;current auxiliary register. ;AR2 is the next auxiliary register. ;Load the TREG with the content of the ;address referenced by AR1, add one to ;the content of AR1, then make AR2 the ;current auxiliary register. ;Multiply TREG by content of address ;referenced by AR2. LT *+,AR2 MPY* 6.3.
Indirect Addressing Mode Table 6–2.
Indirect Addressing Mode Table 6–3.
Indirect Addressing Mode 6.3.5 Examples of Indirect Addressing In Example 6–7, when the ADD instruction is fetched from program memory, the instruction register is loaded with the value shown. Example 6–7. No Increment or Decrement ADD *,8 ;Add to the accumulator the content of the ;data-memory address referenced by the ;current auxiliary register. The data ;is left-shifted 8 bits before being added.
Indirect Addressing Mode Example 6–9. Decrement by 1 ADD *–,8 ;Operates as in Example 6–7, but in ;addition, the current auxiliary register ;is decremented by one. Example 6–10. Increment by Index Amount ADD *0+,8 ;Operates as in Example 6–7, but in ;addition, the content of register AR0 ;is added to the current auxiliary ;register. Example 6–11.
Indirect Addressing Mode 6.3.6 Modifying Auxiliary Register Content The LAR, ADRK, SBRK, and MAR instructions are specialized instructions for changing the content of an auxiliary register (AR): - The LAR instruction loads an AR. The ADRK instruction adds an immediate value to an AR; SBRK subtracts an immediate value. The MAR instruction can increment or decrement an AR value by one or by an index amount. However, you are not limited to these four instructions.
Chapter 7 Assembly Language Instructions The ’C2xx instruction set supports numerically intensive signal-processing operations as well as general-purpose applications such as multiprocessing and high-speed control. The ’C2xx instruction set is compatible with the ’C2x instruction set; code written for the ’C2x can be reassembled to run on the ’C2xx. The ’C5x instruction set is a superset of that of the ’C2xx; thus, code written for the ’C2xx can be upgraded to run on a ’C5x.
Instruction Set Summary 7.
Instruction Set Summary IAAA AAAA (One I followed by seven As) The I at the left represents a bit that reflects whether direct addressing (I = 0) or indirect addressing (I = 1) is being used. When direct addressing is used, the seven As are the seven least significant bits (LSBs) of a data memory address. For indirect addressing, the seven As are bits that control auxiliary register manipulation (see Section 6.3, Indirect Addressing Mode, p. 6-9).
Instruction Set Summary ZLVC ZLVC Two 4-bit fields — each representing the following conditions: ACC = 0 ACC < 0 Overflow Carry Z L V C A conditional instruction contains two of these 4-bit fields. The 4-LSB field of the instruction is a mask field. A 1 in the corresponding mask bit indicates that condition is being tested. For example, to test for ACC ≥ 0, the Z and L fields are set, and the V and C fields are not set.
Instruction Set Summary Table 7–1.
Instruction Set Summary Table 7–1.
Instruction Set Summary Table 7–2.
Instruction Set Summary Table 7–3.
Instruction Set Summary Table 7–4.
Instruction Set Summary Table 7–5.
Instruction Set Summary Table 7–6.
How To Use the Instruction Descriptions 7.2 How To Use the Instruction Descriptions Section 7.3 contains detailed information on the instruction set. The description for each instruction presents the following categories of information: 7.2.1 Syntax Operands Opcode Execution Status Bits Description Words Cycles Examples Syntax Each instruction begins with a list of the available assembler syntax expressions and the addressing mode type(s) for each expression.
How To Use the Instruction Descriptions [, x] Operand x is optional. Example: For the syntax: ADD dma, [, shift] you must supply dma, as in the instruction: ADD 7h and you have the option of adding a shift value, as in the instruction: ADD 7h, 5 [, x1 [, x2]] Operands x1 and x2 are optional, but you cannot include x2 without also including x1.
How To Use the Instruction Descriptions 7.2.2 Operands Operands can be constants, or assembly-time expressions referring to memory, I/O ports, register addresses, pointers, shift counts, and a variety of other constants. The operands category for each instruction description defines the variables used for and/or within operands in the syntax expressions.
How To Use the Instruction Descriptions The field called dma contains the value dma, which is defined in the operands category. The contents of the fields ARU, N, and NAR are derived from the operands ind and n but do not directly correspond to those operands; therefore, a note directs you to the appropriate section for more details. 7.2.4 Execution The execution category presents an instruction operation sequence that describes the processing that takes place when the instruction is executed.
How To Use the Instruction Descriptions 7.2.7 Words The words category specifies the number of memory words (one or two) required to store the instruction. When the number of words depends on the addressing mode used for an instruction, the words category specifies which addressing modes require one word and which require two words. 7.2.
How To Use the Instruction Descriptions If an instruction requires memory operand(s), the rows in the table indicate the location(s) of the operand(s), as defined here: DARAM The operand is in internal dual-access RAM. SARAM The operand is in internal single-access RAM. External The operand is in external memory. For the RPT mode execution, n indicates the number of times a given instruction is repeated by an RPT instruction.
How To Use the Instruction Descriptions The instruction-cycle timings are based on the following assumptions: - 7.2.9 At least the next four instructions are fetched from the same memory section (internal or external) that was used to fetch the current instruction (except in the case of PC discontinuity instructions, such as B, CALL, etc.) In the single-execution mode, there is no pipeline conflict between the current instruction and the instructions immediately preceding or following that instruction.
How To Use the Instruction Descriptions - The instruction also specifies that AR0 will be the next auxiliary register; therefore, after the instruction ARP = 0. Because no carry is generated during the addition, the carry bit (C) becomes 0.
Instruction Descriptions 7.3 Instruction Descriptions This section contains detailed information on the instruction set for the ’C2xx (For a summary of the instruction set, see Section 7.1.) The instructions are presented alphabetically, and the description for each instruction presents the following categories of information: - Syntax Operands Opcode Execution Status Bits Description Words Cycles Examples For a description of how to use each of these categories, see Section 7.2.
Absolute Value of Accumulator Syntax ABS Operands None 15 1 Opcode 14 0 13 1 12 1 11 1 Execution Increment PC, then ... |(ACC)| → ACC; 0 → C Status Bits Affected by OVM 10 1 9 1 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 ABS 0 0 Affects C and OV This instruction is not affected by SXM Description If the contents of the accumulator are greater than or equal to zero, the accumulator is unchanged by the execution of ABS.
ABS Absolute Value of Accumulator Example 1 ABS Before Instruction Example 2 ACC X C ACC X C 1234h After Instruction ACC 0 C ACC 0 C ABS Before Instruction Example 3 ABS 0FFFFFFFFh After Instruction ACC X C 80000000h After Instruction ACC X OV ABS 0 C 7FFFFFFFh 1 OV ;(OVM = 0) Before Instruction ACC X C X OV 7-22 1h ;(OVM = 1) Before Instruction Example 4 1234h 80000000h After Instruction ACC 0 C 1 OV 80000000h
ADD Add to Accumulator Syntax ADD dma [ , shift ] ADD dma, 16 ADD ind [ , shift [ , ARn] ] ADD ind, 16 [ , ARn] ADD #k ADD #lk [ , shift ] Operands dma: shift: n: k: lk: ind: Opcode Direct addressing Direct with left shift of 16 Indirect addressing Indirect with left shift of 16 Short immediate addressing Long immediate addressing 7 LSBs of the data-memory address Left shift value from 0 to 15 (defaults to 0) Value from 0 to 7 designating the next auxiliary register 8-bit short immediate value 16-bi
ADD Add to Accumulator Execution Increment PC, then ...
ADD Add to Accumulator Cycles Cycles for a Single ADD Instruction (Using Direct and Indirect Addressing) Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 2† 1+p External 1+d 1+d 1+d 2+d+p † If the operand and the code are in the same SARAM block Cycles for a Repeat (RPT) Execution of an ADD Instruction (Using Direct and Indirect Addressing) Program Operand ROM DARAM SARAM External DARAM n n n n+p n+p n+1+p+nd SARAM n n n, n+1† External n+nd n+nd
ADD Add to Accumulator Example 3 ADD #1h ;Add short immediate Before Instruction ACC Example 4 ADD X C 2h #1111h,1 After Instruction ACC 0 C ;Add long immediate with shift of 1 Before Instruction ACC 7-26 X C 03h 2h After Instruction ACC 0 C 2224h
Add to Accumulator With Carry Syntax ADDC dma ADDC ind [, ARn] Operands dma: n: ind: ADDC Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– ADDC dma Opcode 15 14 13 12 11 10 9 8 7 0 1 1 0 0 0 0 0 0 6 5 4 3 2 1 0 1 0 dma ADDC ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 1 0 0 0 0 0 1 Note: 6 5 4 ARU 3 2
ADDC Add to Accumulator With Carry Cycles for a Repeat (RPT) Execution of an ADDC Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+p+nd † If the operand and the code are in the same SARAM block Example 1 ADDC DAT300 ;(DP = 6: addresses 0300h–037Fh; ;DAT300 is a label for 300h) Before Instruction Data Memory 300h ACC Example 2 ADDC 1 C *–,AR4 After Instruction 04h Data Memory 300h 13h ACC 04h 0 C ;(OVM
Add to Accumulator With Sign Extension Suppressed Syntax ADDS dma ADDS ind [, ARn] Operands dma: n: ind: ADDS Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– ADDS dma Opcode 15 14 13 12 11 10 9 8 7 0 1 1 0 0 0 1 0 0 6 5 4 3 2 1 0 2 1 0 dma ADDS ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 1 0 0 0 1 0 1 Not
ADDS Add to Accumulator With Sign Extension Suppressed Cycles for a Repeat (RPT) Execution of an ADDS Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+p+nd † If the operand and the code are in the same SARAM block Example 1 ADDS 0 ;(DP = 6: addresses 0300h–037Fh) Before Instruction Data Memory 300h ACC Example 2 ADDS 0F006h X C 00000003h After Instruction Data Memory 300h ACC 0F006h 0 C * Before Instructio
ADDT Add to Accumulator With Shift Specified by TREG Syntax ADDT dma ADDT ind [, ARn] Operands dma: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– ADDT dma Opcode 15 14 13 12 11 10 9 8 7 0 1 1 0 0 0 1 1 0 6 5 4 3 2 1 0 1 0 dma ADDT ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 1 0 0 0 1 1 1 Note: 6
ADDT Add to Accumulator With Shift Specified by TREG Cycles for a Repeat (RPT) Execution of an ADDT Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+p+nd † If the operand and the code are in the same SARAM block Example 1 ADDT 127 ;(DP = 4: addresses 0200h–027Fh, ;SXM = 0) Before Instruction Data Memory 027Fh 09h TREG ACC X After Instruction Data Memory 027Fh 0FF94h TREG 0F715h ACC C Example 2 ADDT *
Add Short-Immediate Value to Auxiliary Register Syntax ADRK #k Operands k: ADRK Short immediate addressing 8-bit short immediate value ADRK #k Opcode 15 14 13 12 11 10 9 8 0 1 1 1 1 0 0 0 7 6 5 4 3 2 1 0 k Execution Increment PC, then ...
AND AND With Accumulator Syntax AND dma AND ind [, ARn] AND #lk [, shift] AND #lk, 16 Operands dma: shift: n: lk: ind: Opcode Direct addressing Indirect addressing Long immediate addressing Long immediate with left shift of 16 7 LSBs of the data-memory address Left shift value from 0 to 15 (defaults to 0) Value from 0 to 7 designating the next auxiliary register 16-bit long immediate value Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– AND dma 15 14 13 12 11 10 9 8 7
AND With Accumulator Status Bits AND None This instruction is not affected by SXM. Description If direct or indirect addressing is used, the low word of the accumulator is ANDed with a data-memory value, and the result is placed in the low word position in the accumulator. The high word of the accumulator is zeroed. If immediate addressing is used, the long-immediate constant can be shifted. During the shift, low-order and high-order bits not filled by the shifted value are zeroed.
AND AND With Accumulator Example 1 AND 16 ;(DP = 4: addresses 0200h–027Fh) Before Instruction Data Memory 0210h 00FFh ACC Example 2 AND 12345678h After Instruction Data Memory 0210h ACC ARP 0 AR0 0301h Data Memory 0301h ACC AND 0FF00h 12345678h After Instruction ARP 0 AR0 0301h Data Memory 0301h ACC 0FF00h 00005600h #00FFh,4 Before Instruction ACC 7-36 00000078h * Before Instruction Example 3 00FFh 12345678h After Instruction ACC 00000670h
Add PREG to Accumulator Syntax APAC Operands None APAC APAC Opcode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 1 0 0 Execution Increment PC, then ... (ACC) + shifted (PREG) → ACC Status Bits Affected by PM and OVM Affects C and OV This instruction is not affected by SXM. Description The contents of PREG are shifted as defined by the PM status bits of the ST1 register (see Table 7–7) and added to the contents of the accumulator.
APAC Add PREG to Accumulator Example APAC ;(PM = 01) Before Instruction PREG ACC 7-38 X C After Instruction 40h PREG 20h ACC 40h 0 C A0h
B Branch Unconditionally Syntax B pma [, ind [, ARn] ] Operands pma: n: ind: Indirect addressing 16-bit program-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– B pma [, ind [, ARn] ] Opcode 15 14 13 12 11 10 9 8 7 0 1 1 1 1 0 0 1 1 6 5 ARU 4 3 2 N 1 0 NAR pma Note: ARU, N, and NAR are defined in Section 6.3, Indirect Addressing Mode (page 6-9).
BACC Branch to Location Specified by Accumulator Syntax BACC Operands None 15 1 Opcode 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 1 4 0 3 0 2 0 1 0 0 0 Execution ACC(15:0) → PC Status Bits None Description Control is passed to the 16-bit address residing in the lower half of the accumulator.
BANZ Branch on Auxiliary Register Not Zero Syntax BANZ pma [, ind [, ARn] ] Operands pma: n: ind: Indirect addressing 16-bit program-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– BANZ pma [, ind [,ARn] ] Opcode 15 14 13 12 11 10 9 8 7 0 1 1 1 1 0 1 1 1 6 5 4 ARU 3 2 N 1 0 NAR pma Note: ARU, N, and NAR are defined in Section 6.3, Indirect Addressing Mode (page 6-9).
BANZ Branch on Auxiliary Register Not Zero Example 1 BANZ PGM0 ;(PGM0 labels program address 0) Before Instruction After Instruction ARP 0 ARP 0 AR0 5h AR0 4h Because the content of AR0 is not zero, the program branches to program address 0 is loaded into the program counter (PC), and the program continues executing from that location. The default auxiliary register operation is a decrement of the current auxiliary register content; thus, AR0 contains 4h at the end of the execution.
Branch Conditionally Syntax BCND pma, cond 1 [,cond 2] [,...] Operands pma: 16-bit program-memory address cond EQ NEQ LT LEQ GT GEQ NC C NOV OV BIO NTC TC UNC 15 1 Opcode BCND Condition ACC = 0 ACC ≠ 0 ACC < 0 ACC ≤ 0 ACC > 0 ACC ≥ 0 C=0 C=1 OV = 0 OV = 1 BIO low TC = 0 TC = 1 Unconditionally 14 1 13 1 12 0 11 0 10 0 9 8 7 TP 6 5 ZLVC 4 3 2 1 ZLVC 0 pma Note: The TP and ZLVC fields are defined on pages 7-3 and 7-4. Execution If cond 1 AND cond 2 AND ...
BCND Branch Conditionally Example BCND PGM191,LEQ,C If the accumulator contents are less than or equal to zero and the carry bit is set, program address 191 is loaded into the program counter, and the program continues to execute from that location. If these conditions do not hold, execution continues from location PC + 2.
BIT Test Bit Syntax BIT dma, bit code BIT ind, bit code [, ARn] Operands dma: bit code: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 15 indicating which bit to test (see Figure 7–1) Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– BIT dma, bit code Opcode 15 14 13 12 0 1 0 0 11 10 9 8 7 bit code 6 5 4 0 3 2 1 0 1 0 dma BIT ind, bit code [ ,ARn
BIT Test Bit Cycles Cycles for a Single BIT Instruction Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 2† 1+p External 1+d 1+d 1+d 2+d+p † If the operand and the code are in the same SARAM block Cycles for a Repeat (RPT) Execution of a BIT Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+p+nd † If the operand and the code are in the same SARAM block Example 1 BIT 0h,15
BITT Test Bit Specified by TREG Syntax BITT dma BITT ind [, ARn] Operands dma: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– BITT dma Opcode 15 14 13 12 11 10 9 8 7 0 1 1 0 1 1 1 1 0 6 5 4 3 2 1 0 1 0 dma BITT ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 1 0 1 1 1 1 1 Note: 6 5 4 3 ARU 2 N
BITT Test Bit Specified by TREG Cycles Cycles for a Single BITT Instruction Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 2† 1+p External 1+d 1+d 1+d 2+d+p † If the operand and the code are in the same SARAM block Cycles for a Repeat (RPT) Execution of an BITT Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+p+nd † If the operand and the code are in the same SARAM block
BLDD Block Move From Data Memory to Data Memory Syntax BLDD source, destination General syntax: BLDD #lk, dma Direct with long immediate source Indirect with long immediate source Direct with long immediate destination Indirect with long immediate destination BLDD #lk, ind [, ARn] BLDD dma, #lk BLDD ind, #lk [, ARn] Operands Opcode dma: n: lk: ind: 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register 16-bit long immediate value Select one of the following sev
BLDD Block Move From Data Memory to Data Memory Execution Increment PC, then ... (PC) → MSTACK lk → PC (source) → destination For indirect, modify (current AR) and (ARP) as specified (PC) + 1 → PC While (repeat counter) ≠ 0: (source) → destination For indirect, modify (current AR) and (ARP) as specified (PC) + 1 → PC (repeat counter) –1 → repeat counter (MSTACK) → PC Status Bits None Description The word in data memory pointed to by source is copied to a data-memory space pointed at by destination.
Block Move From Data Memory to Data Memory BLDD Cycles Cycles for a Single BLDD Instruction Operand ROM DARAM SARAM External Source: DARAM Destination: DARAM 3 3 3 3+2p Source: SARAM Destination: DARAM 3 3 3 3+2p Source: External Destination: DARAM 3+dsrc 3+dsrc 3+dsrc 3+dsrc +2p Source: DARAM Destination: SARAM 3 3 3 4† 3+2p Source: SARAM Destination: SARAM 3 3 3 4† 3+2p Source: External Destination: SARAM 3+dsrc 3+dsrc 3+dsrc 4+dsrc † 3+dsrc +2p Source: DARAM Destinati
BLDD Block Move From Data Memory to Data Memory Cycles for a Repeat (RPT) Execution of a BLDD Instruction Operand ROM DARAM SARAM External Source: DARAM n+2 Destination: DARAM n+2 n+2 n+2+2p Source: SARAM n+2 Destination: DARAM n+2 n+2 n+2+2p Source: External n+2+ndsrc Destination: DARAM n+2+ndsrc n+2+ndsrc n+2+ndsrc +2p Source: DARAM Destination: SARAM n+2 n+2 n+2 n+4† n+2+2p Source: SARAM Destination: SARAM n+2 2n‡ n+2 2n‡ n+2 2n‡ n+4† 2n+2§ n+2+2p 2n+2p‡ Source: External Dest
Block Move From Data Memory to Data Memory Example 1 BLDD #300h,20h ;(DP = 6) Before Instruction Data Memory 300h 0h 320h Example 2 BLDD BLDD 0Fh After Instruction Data Memory 300h 0h 320h 0h *+,#321h,AR3 Before Instruction ARP 2 AR2 After Instruction ARP 3 302h 301h AR2 Data Memory 301h 01h Data Memory 301h 01h 321h 0Fh 321h 01h Assembly Language Instructions 7-53
BLPD Block Move From Program Memory to Data Memory Syntax BLPD source, destination General syntax: BLPD #pma, dma Direct with long immediate source Indirect with long immediate source BLPD #pma, ind [, ARn] Operands Opcode pma: dma: n: ind: 16-bit program-memory address 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– BLPD #pma, dma 15 14 13 12 11 10 9 8 7 1 0 1 0 0 1 0
Block Move From Program Memory to Data Memory Description BLPD A word in program memory pointed to by the source is copied to data-memory space pointed to by destination. The first word of the source space is pointed to by a long-immediate value. The data-memory destination space is pointed to by a data-memory address or auxiliary register pointer. Not all source/destination combinations of pointer types are valid. RPT can be used with the BLPD instruction to move consecutive words.
BLPD Block Move From Program Memory to Data Memory Cycles Cycles for a Single BLPD Instruction Operand ROM DARAM SARAM External Source: DARAM/ROM Destination: DARAM 3 3 3 3+2pcode Source: SARAM Destination: DARAM 3 3 3 3+2pcode Source: External Destination: DARAM 3+psrc 3+psrc 3+psrc 3+psrc +2pcode Source: DARAM/ROM Destination: SARAM 3 3 3 4† 3+2pcode Source: SARAM Destination: SARAM 3 3 3 4† 3+2pcode Source: External Destination: SARAM 3+psrc 3+psrc 3+psrc 4+psrc † 3+psrc
Block Move From Program Memory to Data Memory BLPD Cycles for a Repeat (RPT) Execution of a BLPD Instruction (Continued) Operand ROM DARAM SARAM External Source: SARAM Destination: SARAM n+2 2n‡ n+2 2n‡ n+2 2n‡ n+4† 2n+2§ n+2+2pcode 2n+2pcode ‡ Source: External Destination: SARAM n+2+npsrc † n+2+npsrc n+2+npsrc n+4+npsrc † n+2+npsrc +2pcode Source: DARAM/ROM 2n+2+nddst Destination: External 2n+2+nddst 2n+2+nddst 2n+2+nddst +2pcode Source: SARAM Destination: External 2n+2+nddst 2n+2+nd
CALA Call Subroutine at Location Specified by Accumulator Syntax CALA Operands None 15 1 Opcode 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 1 4 1 3 0 2 0 1 0 0 0 Execution PC + 1 → TOS ACC(15:0) → PC Status Bits None Description The current program counter (PC) is incremented and pushed onto the top of the stack (TOS). Then, the contents of the lower half of the accumulator are loaded into the PC. Execution continues at this address.
CALL Call Unconditionally Syntax CALL pma [, ind [, ARn] ] Operands pma: n: ind: Indirect addressing 16-bit program-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– CALL pma [, ind [, ARn] ] Opcode 15 14 13 12 11 10 9 8 7 0 1 1 1 1 0 1 0 1 6 5 4 ARU 3 2 N 1 0 NAR pma Note: ARU, N, and NAR are defined in Section 6.3, Indirect Addressing Mode (page 6-9).
CC Call Conditionally Syntax CC pma, condĂ1 [,condĂ2] [,...] Operands pma: cond EQ NEQ LT LEQ GT GEQ NC C NOV OV BIO NTC TC UNC 15 1 Opcode 16-bit program-memory address Condition ACC = 0 ACC ≠ 0 ACC < 0 ACC ≤ 0 ACC > 0 ACC ≥ 0 C=0 C=1 OV = 0 OV = 1 BIO low TC = 0 TC = 1 Unconditionally 14 1 13 1 12 0 11 1 10 0 9 8 7 TP 6 5 ZLVC 4 3 2 1 ZLVC 0 pma Note: The TP and ZLVC fields are defined on pages 7-3 and 7-4. Execution If condĂ1 AND condĂ2 AND ...
Call Conditionally Example CC CC PGM191,LEQ,C If the accumulator contents are less than or equal to zero and the carry bit is set, 0BFh (191) is loaded into the program counter, and the program continues to execute from that location. If the conditions are not met, execution continues at the instruction following the CC instruction.
CLRC Clear Control Bit Syntax CLRC control bit Operands control bit: Opcode CLRC C 15 1 14 0 Select one of the following control bits: C Carry bit of status register ST1 CNF RAM configuration control bit of status register ST1 INTM Interrupt mode bit of status register ST0 OVM Overflow mode bit of status register ST0 SXM Sign-extension mode bit of status register ST1 TC Test/control flag bit of status register ST1 XF XF pin status bit of status register ST1 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6
Clear Control Bit Words CLRC 1 Cycles Cycles for a Single CLRC Instruction ROM DARAM SARAM External 1 1 1 1+p Cycles for a Repeat (RPT) Execution of a CLRC Instruction Example ROM DARAM SARAM External n n n n+p CLRC TC ;(TC is bit 11 of ST1) Before Instruction ST1 x9xxh After Instruction ST1 Assembly Language Instructions x1xxh 7-63
CMPL Complement Accumulator Syntax CMPL Operands None 15 1 Opcode 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1 Execution Increment PC, then ... (ACC) → ACC Status Bits None Description The contents of the accumulator are replaced with its logical inversion (1s complement). The carry bit is unaffected.
Compare Auxiliary Register With AR0 Syntax CMPR CM Operands CM: 15 1 Opcode CMPR Value from 0 to 3 14 0 13 1 12 1 11 1 10 1 9 1 8 1 7 0 6 1 5 0 4 0 3 0 2 1 1 0 CM Execution Increment PC, then ... Compare (current AR) to (AR0) and place the result in the TC bit of status register ST1. Status Bits Affects TC This instruction is not affected by SXM. It does not affect SXM.
DMOV Data Move in Data Memory Syntax DMOV dma DMOV ind [, ARn] Operands dma: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– DMOV dma Opcode 15 14 13 12 11 10 9 8 7 0 1 1 1 0 1 1 1 0 6 5 4 3 2 1 0 2 1 0 dma DMOV ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 1 1 0 1 1 1 1 Note: 6 5 ARU 4 3 N NAR
Data Move in Data Memory Cycles DMOV Cycles for a Single DMOV Instruction Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 3† 1+p External‡ 2+2d 2+2d 2+2d 5+2d+p † If the operand and the code are in the same SARAM block ‡ If used on external memory, DMOV reads the specified memory location but performs no operations.
IDLE Idle Until Interrupt Syntax IDLE Operands None 15 1 Opcode 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 1 4 0 3 0 2 0 1 1 0 0 Execution Increment PC, then wait for unmasked or nonmaskable hardware interrupt. Status Bits Affected by INTM Description The IDLE instruction forces the program being executed to halt until the CPU receives a request from an unmasked hardware interrupt (external or internal), NMI, or reset.
IN Input Data From Port Syntax IN dma, PA IN ind, PA [, ARn] Operands dma: n: PA: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register 16-bit I/O port or I/O-mapped register address Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– IN dma , PA Opcode 15 14 13 12 11 10 9 8 7 1 0 1 0 1 1 1 1 0 6 5 4 3 2 1 0 2 1 0 dma PA IN ind ,PA [,ARn] 15 14 13 12 11 10 9 8 7
IN Input Data From Port Cycles Cycles for a Single IN Instruction Program Operand ROM DARAM SARAM External Destination: DARAM 2+iosrc 2+iosrc 2+iosrc 3+iosrc +2pcode Destination: SARAM 2+iosrc 2+iosrc 2+iosrc 3+iosrc † 3+iosrc +2pcode Destination: External 3+ddst +iosrc 3+ddst +iosrc 3+ddst +iosrc 6+ddst +iosrc +2pcode † If the operand and the code are in the same SARAM block Cycles for a Repeat (RPT) Execution of an IN Instruction Program Operand ROM DARAM SARAM External Destin
INTR Software Interrupt Syntax INTR K Operands K: 15 1 Opcode Value from 0 to 31 that indicates the interrupt vector location to branch to 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 Execution (PC) + 1 → stack corresponding interrupt vector location → PC Status Bits Affects INTM 5 1 4 3 2 K 1 0 This instruction is not affected by INTM. Description The processor has locations for 32 interrupt vectors; each location is represented by a value K from 0 to 31.
LACC Load Accumulator With Shift Syntax LACC dma [, shift] LACC dma, 16 LACC ind [, shift [, ARn] ] LACC ind, 16[, ARn] LACC #lk [, shift] Operands dma: shift: n: lk: ind: Opcode Direct addressing Direct with left shift of 16 Indirect addressing Indirect with left shift of 16 Long immediate addressing 7 LSBs of the data-memory address Left shift value from 0 to 15 (defaults to 0) Value from 0 to 7 designating the next auxiliary register 16-bit long immediate value Select one of the following seven o
Load Accumulator With Shift Execution LACC Increment PC, then ... Event (data-memory address) × 2shift → ACC Addressing mode Direct or indirect (data-memory address) × 216 → ACC Direct or indirect (shift of 16) lk × 2shift → ACC Long immediate Status Bits Affected by SXM Description The contents of the specified data-memory address or a 16-bit constant are left shifted and loaded into the accumulator. During shifting, low-order bits are zero filled.
LACC Load Accumulator With Shift Example 1 LACC 6,4 ;(DP = 8: addresses 0400h–047Fh, ;SXM = 0) Before Instruction Data Memory 406h ACC Example 2 LACC 01h X C *,4 012345678h After Instruction Data Memory 406h ACC 01h X C ;(SXM = 0) Before Instruction ARP 2 AR2 Data Memory 300h ACC Example 3 LACC X C After Instruction ARP 2 0300h AR2 0300h 0FFh Data Memory 300h 12345678h 0FFh ACC X C ACC X C 0FF0h #0F000h,1 ;(SXM = 1) Before Instruction ACC 7-74 10h X C 012345678h After
LACL Load Low Accumulator and Clear High Accumulator Syntax LACL dma LACL ind [, ARn] LACL #k Operands dma: n: k: ind: Direct addressing Indirect addressing Short immediate 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register 8-bit short immediate value Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– LACL dma Opcode 15 14 13 12 11 10 9 8 7 0 1 1 0 1 0 0 1 0 6 5 4 3 2 1 0 1 0 dma LACL ind [, ARn] 15 14 13 1
LACL Load Low Accumulator and Clear High Accumulator Cycles Cycles for a Single LACL Instruction (Using Direct and Indirect Addressing) Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 2† 1+p External 1+d 1+d 1+d 2+d+p † If the operand and the code are in the same SARAM block Cycles for a Repeat (RPT) Execution of an LACL Instruction (Using Direct and Indirect Addressing) Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p
Load Low Accumulator and Clear High Accumulator Example 3 LACL LACL #10h Before Instruction ACC X C 7FFFFFFFh After Instruction ACC X C Assembly Language Instructions 010h 7-77
LACT Load Accumulator With Shift Specified by TREG Syntax LACT dma LACT ind [, ARn] Operands dma: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– LACT dma Opcode 15 14 13 12 11 10 9 8 7 0 1 1 0 1 0 1 1 0 6 5 4 3 2 1 0 1 0 dma LACT ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 1 0 1 0 1 1 1 Note: Exe
LACT Load Accumulator With Shift Specified by TREG Cycles Cycles for a Single LACT Instruction Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 2† 1+p External 1+d 1+d 1+d 2+d+p † If the operand and the code are in the same SARAM block Cycles for a Repeat (RPT) Execution of an LACT Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+p+nd † If the operand and the code are in the
LAR Load Auxiliary Register Syntax LAR ARx, dma LAR ARx, ind [, ARn] LAR ARx, #k LAR ARx, #lk Operands x: dma: k: lk: n: ind: Opcode Direct addressing Indirect addressing Short immediate addressing Long immediate addressing Value from 0 to 7 designating the auxiliary register to be loaded 7 LSBs of the data-memory address 8-bit short immediate value 16-bit long immediate value Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *
Load Auxiliary Register Description LAR The contents of the specified data-memory address or an 8-bit or 16-bit constant are loaded into the specified auxiliary register (ARx). The specified constant is acted upon like an unsigned integer, regardless of the value of SXM. The LAR and SAR (store auxiliary register) instructions can be used to load and store the auxiliary registers during subroutine calls and interrupts.
LAR Load Auxiliary Register Example 1 LAR AR0,16 ;(DP = 6: addresses 0300h–037Fh) Before Instruction Example 2 LAR After Instruction Data Memory 310h 18h Data Memory 310h 18h AR0 6h AR0 18h AR4,*– Before Instruction ARP 4 After Instruction ARP 4 Data Memory 300h 32h Data Memory 300h 32h AR4 300h AR4 32h Note: LAR in the indirect addressing mode ignores any AR modifications if the AR specified by the instruction is the same as that pointed to by the ARP.
Load Data Page Pointer Syntax LDP dma LDP ind [, ARn] LDP #k Operands dma: n: k: ind: LDP Direct addressing Indirect addressing Short immediate addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register 9-bit short immediate value Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– LDP dma Opcode 15 14 13 12 11 10 9 8 7 0 0 0 0 1 1 0 1 0 6 5 4 3 2 1 0 1 0 dma LDP ind [, ARn] 15 14 13 12 11 10 9 8 7
LDP Load Data Page Pointer Cycles Cycles for a Single LDP Instruction (Using Direct and Indirect Addressing) Program Operand ROM DARAM SARAM External DARAM 2 2 2 2+pcode SARAM 2 2 2, 3† 2+pcode External 2+dsrc 2+dsrc 2+dsrc 3+dsrc +pcode † If the operand and the code are in the same SARAM block Cycles for a Repeat (RPT) Execution of an LDP Instruction (Using Direct and Indirect Addressing) Program Operand ROM DARAM SARAM External DARAM 2n 2n 2n 2n+pcode SARAM 2n 2n 2n, 2n
Load Product Register High Word Syntax LPH dma LPH ind [, ARn] Operands dma: n: ind: LPH Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– LPH dma Opcode 15 14 13 12 11 10 9 8 7 0 1 1 1 0 1 0 1 0 6 5 4 3 2 1 0 1 0 dma LPH ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 1 1 0 1 0 1 1 Note: 6 5 ARU 4 3 2 N
LPH Load Product Register High Word Cycles for a Repeat (RPT) Execution of an LPH Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+p+nd † If the operand and the code are in the same SARAM block Example 1 LPH DAT0 ;(DP = 4) Before Instruction Data Memory 200h PREG Example 2 LPH 0F79Ch 30079844h After Instruction Data Memory 200h PREG 0F79C9844h *,AR6 Before Instruction After Instruction ARP 5 ARP 6 AR5
LST Load Status Register Syntax LST #m, dma LST #m, ind [, ARn] Operands dma: n: m: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following: 0 Indicates that ST0 will be loaded 1 Indicates that ST1 will be loaded Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– ind: LST #0, dma Opcode 15 14 13 12 11 10 9 8 7 0 0 0 0 1 1 1 0 0 6 5 4 3 2 1 0 1 0 dma
LST Load Status Register Figure 7–4. LST #1 Operation 15 ST0 14 13 ARP ↑ ↑ ↑ 15 14 13 12 11 10 9 OV OVM 1 INTM 8 12 11 10 9 7 6 5 4 3 2 1 0 3 2 1 0 ↓ ↓ DP 8 7 6 5 4 Data ↓ ↓ ↓ ↓ ↓ ↓ ↓ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 CNF TC SXM C 1 1 1 1 XF 1 1 ST1 ARB Status Bits ↓ 1 0 PM Affects ARB, ARP, OV, OVM, DP, CNF, TC, SXM, C, XF, and PM This instruction does not affect INTM.
Load Status Register LST Cycles for a Repeat (RPT) Execution of an LST Instruction Program Operand ROM DARAM SARAM External DARAM 2n 2n 2n 2n+pcode SARAM 2n 2n 2n, 2n+1† 2n+pcode External 2n+ndsrc 2n+ndsrc 2n+ndsrc 2n+1+ndsrc +pcode † If the operand and the code are in the same SARAM block Example 1 Example 2 MAR LST LST *,AR0 #0,*,AR1 ;The data memory word addressed by the ;contents of auxiliary register AR0 is ;loaded into status register ST0,except ;for the INTM bit.
LST Load Status Register Example 4 LST #1,00h ;(DP = 6) ;Note that the ARB is loaded with ;the new ARP value.
LT Load TREG Syntax LT dma LT ind [, ARn] Operands dma: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– LT dma Opcode 15 14 13 12 11 10 9 8 7 0 1 1 1 0 0 1 1 0 6 5 4 3 2 1 0 2 1 0 dma LT ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 1 1 0 0 1 1 1 Note: 6 5 ARU 4 3 N NAR ARU, N, and NAR are def
LT Load TREG Cycles for a Repeat (RPT) Execution of an LT Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+p+nd † If the operand and the code are in the same SARAM block Example 1 LT 24 ;(DP = 8: addresses 0400h–047Fh) Before Instruction Example 2 LT Data Memory 418h TREG After Instruction 62h Data Memory 418h 62h 3h TREG 62h *,AR3 Before Instruction 7-92 After Instruction ARP 2 ARP 3 AR2 418h
LTA Load TREG and Accumulate Previous Product Syntax LTA dma LTA ind [, ARn] Operands dma: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– LTA dma Opcode 15 14 13 12 11 10 9 8 7 0 1 1 1 0 0 0 0 0 6 5 4 3 2 1 0 2 1 0 dma LTA ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 1 1 0 0 0 0 1 Note: 6 5 ARU
LTA Load TREG and Accumulate Previous Product Cycles for a Repeat (RPT) Execution of an LTA Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+p+nd † If the operand and the code are in the same SARAM block Example 1 LTA 36 ;(DP = 6: addresses 0300h–037Fh, ;PM =0: no shift of product) Before Instruction Data Memory 324h TREG PREG ACC Example 2 LTA X C *,AR5 After Instruction 62h Data Memory 324h 62h 3h TRE
LTD Load TREG, Accumulate Previous Product, and Move Data Syntax LTD dma LTD ind [, ARn] Operands dma: n: ind: Opcode Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– LTD dma 15 14 13 12 11 10 9 8 7 0 1 1 1 0 0 1 0 0 6 5 4 3 2 1 0 2 1 0 dma LTD ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 1 1 0 0 1 0 1 Note:
LTD Load TREG, Accumulate Previous Product, and Move Data Words 1 Cycles Cycles for a Single LTD Instruction Program Operand ROM DARAM SARAM External‡ DARAM 1 1 1 1+p SARAM 1 1 1, 3† 1+p External 2+2d 2+2d 2+2d 5+2d+p † If the operand and the code are in the same SARAM block ‡ If the LTD instruction is used with external memory, the data move will not occur. (The previous product will be accumulated, and the TREG will be loaded.
Load TREG, Accumulate Previous Product, and Move Data Example 2 LTD *,AR3 ;(PM = 0) Before Instruction After Instruction ARP 1 ARP 3 AR1 3FEh AR1 3FEh Data Memory 3FEh 62h Data Memory 3FEh 62h Data Memory 3FFh 0h Data Memory 3FFh 62h TREG 3h TREG 62h PREG 0Fh PREG 0Fh ACC Note: LTD X C 5h ACC 0 C 14h The data move function for LTD can occur only within on-chip data memory RAM blocks.
LTP Load TREG and Store PREG in Accumulator Syntax LTP dma LTP ind [, ARn] Operands dma: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– LTP dma Opcode 15 14 13 12 11 10 9 8 7 0 1 1 1 0 0 0 1 0 6 5 4 3 2 1 0 1 0 dma LTP ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 1 1 0 0 0 1 1 Note: 6 5 ARU 4 3
Load TREG and Store PREG in Accumulator LTP Cycles for a Repeat (RPT) Execution of an LTP Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+p+nd † If the operand and the code are in the same SARAM block Example 1 LTP 36 ;(DP = 6: addresses 0300h–037Fh, ;PM = 0: no shift of product) Before Instruction Data Memory 324h TREG PREG ACC Example 2 LTP After Instruction 62h Data Memory 324h 62h 3h TREG 62h 0Fh
LTS Load TREG and Subtract Previous Product Syntax LTS dma LTS ind [, ARn] Operands dma: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– LTS dma Opcode 15 14 13 12 11 10 9 8 7 0 1 1 1 0 1 0 0 0 6 5 4 3 2 1 0 2 1 0 dma LTS ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 1 1 0 1 0 0 1 Note: 6 5 ARU 4
LTS Load TREG and Subtract Previous Product Cycles for a Repeat (RPT) Execution of an LTS Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+p+nd † If the operand and the code are in the same SARAM block Example 1 LTS DAT36 ;(DP = 6: addresses 0300h–037Fh, ;PM = 0: no shift of product) Before Instruction Data Memory 324h TREG PREG LTS 62h 62h 3h TREG 62h 0Fh PREG X C 05h ACC *,AR2 ;(PM = 0) ACC Exam
MAC Multiply and Accumulate Syntax MAC pma, dma MAC pma, ind [, ARn] Operands dma: pma: n: ind: Opcode Direct addressing Indirect addressing 7 LSBs of the data-memory address 16-bit program-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– MAC pma, dma 15 14 13 12 11 10 9 8 7 1 0 1 0 0 0 1 0 0 6 5 4 3 2 1 0 2 1 0 dma pma MAC pma, ind [, ARn] 15 14 13 12 11 10 9 8 7 1
Multiply and Accumulate Description MAC The MAC instruction: - Adds the previous product, shifted as defined by the PM status bits, to the accumulator. The carry bit is set (C = 1) if the result of the addition generates a carry and is cleared (C = 0) if it does not generate a carry. Loads the TREG with the content of the specified data-memory address. Multiplies the data-memory value in the TREG by the contents of the specified program-memory address.
MAC Multiply and Accumulate Cycles Cycles for a Single MAC Instruction Operand ROM DARAM SARAM External Operand 1: DARAM/ ROM Operand 2: DARAM 3 3 3 3+2pcode Operand 1: SARAM Operand 2: DARAM 3 3 3 3+2pcode Operand 1: External Operand 2: DARAM 3+pop1 3+pop1 3+pop1 3+pop1 +2pcode Operand 1: DARAM/ ROM Operand 2: SARAM 3 3 3 3+2pcode Operand 1: SARAM Operand 2: SARAM 3 4† 3 4† 3 4† 3+2pcode 4+2pcode † Operand 1: External Operand 2: SARAM 3+pop1 3+pop1 3+pop1 3+pop1 +2pcode
Multiply and Accumulate MAC Cycles for a Repeat (RPT) Execution of an MAC Instruction (Continued) Operand ROM DARAM SARAM External Operand 1: DARAM/ ROM Operand 2: SARAM n+2 n+2 n+2 n+2+2pcode Operand 1: SARAM Operand 2: SARAM n+2 2n+2† n+2 2n+2† n+2 2n+2† n+2+2pcode 2n+2† Operand 1: External Operand 2: SARAM n+2+npop1 n+2+npop1 n+2+npop1 n+2+npop1 +2pcode Operand 1: DARAM/ ROM Operand 2: External n+2+ndop2 n+2+ndop2 n+2+ndop2 n+2+ndop2 +2pcode Operand 1: SARAM Operand 2: External
MACD Multiply and Accumulate With Data Move Syntax MACD pma, dma MACD pma, ind [, ARn] Operands dma: pma: n: ind: Opcode Direct addressing Indirect addressing 7 LSBs of the data-memory address 16-bit program-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– MACD pma, dma 15 14 13 12 11 10 9 8 7 1 0 1 0 0 0 1 1 0 6 5 4 3 2 1 0 2 1 0 dma pma MACD pma, ind [, ARn] 15 14 13 12
Multiply and Accumulate With Data Move Status Bits Affected by PM and OVM Description The MACD instruction: - MACD Affects C and OV Adds the previous product, shifted as defined by the PM status bits, to the accumulator. The carry bit is set (C = 1) if the result of the addition generates a carry and is cleared (C = 0) if it does not generate a carry. Loads the TREG with the content of the specified data-memory address.
MACD Multiply and Accumulate With Data Move Cycles for a Single MACD Instruction (Continued) Operand ROM DARAM SARAM External Operand 1: External Operand 2: DARAM 3+pop1 3+pop1 3+pop1 3+pop1 +2pcode Operand 1: DARAM/ ROM Operand 2: SARAM 3 3 3 3+2pcode Operand 1: SARAM Operand 2: SARAM 3 3 3 4† 5‡ 3+2pcode 4+2pcode † Operand 1: External Operand 2: SARAM 3+pop1 3+pop1 3+pop1 3+pop1 +2pcode Operand 1: DARAM/ ROM Operand 2: External§ 3+dop2 3+dop2 3+dop2 3+dop2 +2pcode Operand 1
Multiply and Accumulate With Data Move MACD Cycles for a Repeat (RPT) Execution of an MACD Instruction (Continued) Operand ROM DARAM SARAM External Operand 1: SARAM Operand 2: SARAM 2n 3n‡ 2n 3n‡ 2n 2n+2† 3n‡ 3n+2§ 2n+2pcode 3n‡ Operand 1: External Operand 2: SARAM 2n+npop1 2n+npop1 2n+npop1 2n+2+npop1 † 2n+npop1 +2pcode Operand 1: DARAM/ ROM Operand 2: External¶ n+2+ndop2 n+2+ndop2 n+2+ndop2 n+2+ndop2 +2pcode Operand 1: SARAM Operand 2: External¶ n+2+ndop2 n+2+ndop2 n+2+ndop2 n+2+
MACD Multiply and Accumulate With Data Move Example 2 MACD 0FF00h,*,AR6 ;(PM = 0, CNF = 1) Before Instruction ARP 5 ARP 6 AR5 308h AR5 308h Data Memory 308h 23h Data Memory 308h 23h Data Memory 309h 18h Data Memory 309h 23h Program Memory FF00h 4h Program Memory FF00h 4h TREG 45h TREG 23h PREG 458972h PREG 8Ch ACC Note: 7-110 After Instruction X C 723EC41h ACC 0 C 76975B3h The data move function for MACD can occur only within on-chip data memory RAM blocks.
MAR Modify Auxiliary Register Syntax MAR dma MAR ind [, ARn] Operands n: ind: Opcode Direct addressing Indirect addressing Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– MAR dma 15 14 13 12 11 10 9 8 7 1 0 0 0 1 0 1 1 0 6 5 4 3 2 1 0 1 0 dma MAR ind [, ARn] 15 14 13 12 11 10 9 8 7 1 0 0 0 1 0 1 1 1 Note: Execution Status Bits Description 6 5 4 ARU 3 2 N NAR ARU
MAR Modify Auxiliary Register Words 1 Cycles Cycles for a Single MAR Instruction ROM DARAM SARAM External 1 1 1 1+p Cycles for a Repeat (RPT) Execution of an MAR Instruction Example 1 ROM DARAM SARAM External n n n n+p MAR *,AR1 ;Load the ARP with 1. Before Instruction Example 2 MAR After Instruction ARP 0 ARP 1 ARB 7 ARB 0 *+,AR5 ;Increment current auxiliary ;register (AR1) and load ARP ;with 5.
MPY Multiply Syntax MPY dma MPY ind [, ARn] MPY #k Operands dma: n: k: ind: Direct addressing Indirect addressing Short immediate addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register 13-bit short immediate value Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– MPY dma Opcode 15 14 13 12 11 10 9 8 7 0 1 0 1 0 1 0 0 0 6 5 4 3 2 1 0 1 0 dma MPY ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 0 1 0
MPY Multiply Cycles Cycles for a Single MPY Instruction (Using Direct and Indirect Addressing) Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 2† 1+p External 1+d 1+d 1+d 2+d+p † If the operand and the code are in the same SARAM block Cycles for a Repeat (RPT) Execution of an MPY Instruction (Using Direct and Indirect Addressing) Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+p+nd † I
Multiply Example 2 MPY *,AR2 Before Instruction MPY After Instruction ARP 1 ARP 2 AR1 40Dh AR1 40Dh Data Memory 40Dh Example 3 MPY 7h Data Memory 40Dh 7h TREG 6h TREG 6h PREG 36h PREG 2Ah #031h Before Instruction After Instruction TREG 2h TREG 2h PREG 36h PREG 62h Assembly Language Instructions 7-115
MPYA Multiply and Accumulate Previous Product Syntax MPYA dma MPYA ind [, ARn] Operands dma: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– MPYA dma Opcode 15 14 13 12 11 10 9 8 7 0 1 0 1 0 0 0 0 0 6 5 4 3 2 1 0 1 0 dma MPYA ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 0 1 0 0 0 0 1 Note: 6 5 4 A
Multiply and Accumulate Previous Product MPYA Cycles for a Repeat (RPT) Execution of an MPYA Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+p+nd † If the operand and the code are in the same SARAM block Example 1 MPYA DAT13 ;(DP = 6, PM = 0) Before Instruction Data Memory 30Dh MPYA 7h TREG 6h TREG 6h PREG 36h PREG 2Ah 54h ACC ACC Example 2 7h After Instruction Data Memory 30Dh X C *,AR4 0 C
MPYS Multiply and Subtract Previous Product Syntax MPYS dma MPYS ind [, ARn] Operands dma: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– MPYS dma Opcode 15 14 13 12 11 10 9 8 7 0 1 0 1 0 0 0 1 0 6 5 4 3 2 1 0 1 0 dma MPYS ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 0 1 0 0 0 1 1 Note: 6 5 4 ARU
Multiply and Subtract Previous Product MPYS Cycles for a Repeat (RPT) Execution of an MPYS Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+p+nd † If the operand and the code are in the same SARAM block Example 1 MPYS DAT13 ;(DP = 6, PM = 0) Before Instruction Data Memory 30Dh MPYS 7h TREG 6h TREG 6h PREG 36h PREG 2Ah 54h ACC ACC Example 2 7h After Instruction Data Memory 30Dh X C *,AR5 1 C 1
MPYU Multiply Unsigned Syntax MPYU dma MPYU ind [, ARn] Operands dma: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– MPYU dma Opcode 15 14 13 12 11 10 9 8 7 0 1 0 1 0 1 0 1 0 6 5 4 3 2 1 0 2 1 0 dma MPYU ind [,ARn] 15 14 13 12 11 10 9 8 7 0 1 0 1 0 1 0 1 1 Note: 6 5 ARU 4 3 N NAR ARU, N,
Multiply Unsigned Cycles MPYU Cycles for a Single MPYU Instruction Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 2† 1+p External 1+d 1+d 1+d 2+d+p † If the operand and the code are in the same SARAM block Cycles for a Repeat (RPT) Execution of an MPYU Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+p+nd † If the operand and the code are in the same SARAM block Example 1
NEG Negate Accumulator Syntax NEG Operands None 15 1 Opcode 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 1 0 0 Execution Increment PC, then ... (ACC) × –1 → ACC Status Bits Affected by OVM Description The content of the accumulator is replaced with its arithmetic complement (2s complement). The OV bit is set when taking the NEG of 8000 0000h. If OVM = 1, the accumulator content is replaced with 7FFF FFFFh. If OVM = 0, the result is 8000 0000h.
Negate Accumulator Example 3 NEG NEG ;(OVM = 1) Before Instruction ACC X C X OV 080000000h After Instruction ACC 0 C 7FFFFFFFh 1 OV Assembly Language Instructions 7-123
NMI Nonmaskable Interrupt Syntax NMI Operands None 15 1 Opcode 14 0 13 1 12 1 Execution (PC) + 1 → stack 24h → PC 1 → INTM Status Bits Affects INTM 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 1 3 0 2 0 1 1 0 0 This instruction is not affected by INTM. Description The NMI instruction forces the program counter to the nonmaskable interrupt vector located at 24h. This instruction has the same effect as the hardware nonmaskable interrupt NMI.
NOP No Operation Syntax NOP Operands None 15 1 Opcode 14 0 13 0 12 0 11 1 10 0 9 1 8 1 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Execution Increment PC Status Bits None Description No operation is performed. The NOP instruction affects only the PC. The NOP instruction is useful to create pipeline and execution delays.
NORM Normalize Contents of Accumulator Syntax NORM ind Operands ind: Opcode Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– NORM ind 15 14 13 12 11 10 9 8 7 1 0 1 0 0 0 0 0 1 Note: Execution Indirect addressing 6 5 ARU 4 3 N 2 1 0 NAR ARU, N, and NAR are defined in Section 6.3, Indirect Addressing Mode (page 6-9). Increment PC, then ...
Normalize Contents of Accumulator NORM Notes: For the NORM instruction, the auxiliary register operations are executed during the fourth phase of the pipeline, the execution phase. For other instructions, the auxiliary register operations take place in the second phase of the pipeline, in the decode phase. Therefore: 1) The auxiliary register values should not be modified by the two instruction words following NORM.
NORM Normalize Contents of Accumulator Example 3 15-Bit Normalization: MAR LAR RPT *,AR1 AR1,#0Fh #14 NORM *– ;Use AR1 to store the exponent. ;Initialize exponent counter. ;15-bit normalization specified (yielding ;a 4-bit exponent and 16-bit mantissa). ;NORM automatically stops shifting when first ;significant magnitude bit is found, ;performing NOPs for the remainder of the ;repeat loops. The method used in Example 2 normalizes a 32-bit number and yields a 5-bit exponent magnitude.
OR OR With Accumulator Syntax OR dma OR ind [, ARn] OR #lk [, shift] OR #lk, 16 Operands dma: shift: n: lk: ind: Opcode Direct addressing Indirect addressing Long immediate addressing Long immediate with left shift of 16 7 LSBs of the data-memory address Left shift value from 0 to 15 (defaults to 0) Value from 0 to 7 designating the next auxiliary register 16-bit long immediate value Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– OR dma 15 14 13 12 11 10 9 8 7 0 1
OR OR With Accumulator Status Bits None This instruction is not affected by SXM. Description An OR operation is performed on the contents of the accumulator and the contents of the addressed data-memory location or a long-immediate value. The long-immediate value may be shifted before the OR operation. The result remains in the accumulator. All bit positions unoccupied by the data operand are zero filled, regardless of the value of the SXM status bit.
OR With Accumulator Example 1 OR DAT8 ;(DP = 8) Before Instruction Data Memory 408h ACC Example 2 X C After Instruction 0F000h Data Memory 408h 100002h ACC 0F000h X C 10F002h OR *,AR0 Before Instruction ARP 1 AR1 Data Memory 300h ACC Example 3 OR X C After Instruction ARP 0 300h AR1 300h 1111h Data Memory 300h 222h ACC 1111h X C 1333h OR #08111h,8 Before Instruction ACC X C 0FF0000h After Instruction ACC X C Assembly Language Instructions 0FF1100h 7-131
OUT Output Data to Port Syntax OUT dma, PA OUT ind, PA [, ARn] Operands dma: PA: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address 16-bit I/O address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– OUT dma, PA Opcode 15 14 13 12 11 10 9 8 0 0 0 0 1 1 0 0 7 6 5 4 0 3 2 1 0 1 0 dma PA OUT ind, PA [, ARn] 15 14 13 12 11 10 9 8 7 0 0 0 0 1 1 0 0 1
Output Data to Port OUT Cycles Cycles for a Single OUT Instruction Program Operand ROM DARAM SARAM External Source: DARAM 3+iodst 3+iodst 3+iodst 5+iodst +2pcode Source: SARAM 3+iodst 3+iodst 3+iodst 4+iodst † 5+iodst +2pcode Source: External 3+dsrc +iodst 3+dsrc +iodst 3+dsrc +iodst 6+dsrc +iodst +2pcode † If the operand and the code are in the same SARAM block Cycles for a Repeat (RPT) Execution of an OUT Instruction Program Operand ROM DARAM SARAM External Destination: DARAM
PAC Load Accumulator With Product Register Syntax PAC Operands None 15 1 Opcode 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 1 0 1 Execution Increment PC, then ... shifted (PREG) → ACC Status Bits Affected by PM Description The content of PREG, shifted as specified by the PM status bits, is loaded into the accumulator.
Pop Top of Stack to Low Accumulator Syntax POP Operands None 15 1 Opcode 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 1 4 1 3 0 2 0 1 1 POP 0 0 Execution Increment PC, then ... (TOS) → ACC(15:0) 0 → ACC(31:16) Pop stack one level Status Bits None Description The content of the top of the stack (TOS) is copied to the low accumulator, and then the stack values move up one level. The upper half of the accumulator is set to all zeros.
POP Pop Top of Stack to Low Accumulator Example POP Before Instruction ACC Stack 7-136 X C After Instruction 82h ACC 45h Stack X C 45h 16h 16h 7h 7h 33h 33h 42h 42h 56h 56h 37h 37h 61h 61h 61h
Pop Top of Stack to Data Memory Syntax POPD dma POPD ind [, ARn] Operands dma: n: ind: POPD Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– POPD dma Opcode 15 14 13 12 11 10 9 8 7 1 0 0 0 1 0 1 0 0 6 5 4 3 2 1 0 1 0 dma POPD ind [,ARn] 15 14 13 12 11 10 9 8 7 1 0 0 0 1 0 1 0 1 Note: 6 5 4 ARU 3 2
POPD Pop Top of Stack to Data Memory Cycles for a Repeat (RPT) Execution of a POPD Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+2† n+p External 2n+nd 2n+nd 2n+nd 2n+2+nd+p † If the operand and the code are in the same SARAM block Example 1 POPD DAT10 ;(DP = 8) Before Instruction Example 2 7-138 POPD Data Memory 40Ah Stack After Instruction 55h Data Memory 40Ah 92h 92h Stack 72h 72h 8h 8h 44h 44h 81h 81h 75h 75h 32h 32h 0A
PSHD Push Data-Memory Value Onto Stack Syntax PSHD dma PSHD ind [, ARn] Operands dma: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– PSHD dma Opcode 15 14 13 12 11 10 9 8 7 0 1 1 1 0 1 1 0 0 6 5 4 3 2 1 0 1 0 dma PSHD ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 1 1 0 1 1 0 1 Note: 6 5 4 ARU 3
PSHD Push Data-Memory Value Onto Stack Cycles for a Repeat (RPT) Execution of a PSHD Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+nd+p † If the operand and the code are in the same SARAM block Example 1 PSHD 127 ;(DP = 3: addresses 0180–01FFh) Before Instruction Data Memory 1FFh Stack Example 2 PSHD 65h 65h 2h Stack 65h 33h 2h 78h 33h 99h 78h 42h 99h 50h 42h 0h 50h 0h 0h Before Instructi
Push Low Accumulator Onto Stack Syntax PUSH Operands None 15 1 Opcode 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 1 4 1 3 1 2 1 PUSH 1 0 0 0 Execution Increment PC, then... Push all stack locations down one level ACC(15:0) → TOS Status Bits None Description The stack values move down one level. Then, the content of the lower half of the accumulator is copied onto the top of the hardware stack. The hardware stack operates as a last-in, first-out stack with eight locations.
RET Return From Subroutine Syntax RET Operands None 15 1 Opcode 14 1 13 1 12 0 11 1 10 1 9 1 8 1 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Execution (TOS) → PC Pop stack one level. Status Bits None Description The contents of the top stack register are copied into the program counter. The remaining stack values are then copied up one level. RET concludes subroutines and interrupt service routines to return program control to the calling or interrupted program sequence.
Return Conditionally Syntax RETC cond 1 [, cond 2] [,...] Operands cond EQ NEQ LT LEQ GT GEQ NC C NOV OV BIO NTC TC UNC RETC Condition ACC = 0 ACC ≠ 0 ACC < 0 ACC ≤ 0 ACC > 0 ACC ≥ 0 C=0 C =1 OV = 0 OV = 1 BIO low TC = 0 TC = 1 Unconditionally ‡ 15 1 Opcode Note: 14 1 13 1 12 0 11 1 10 1 9 8 TP 7 6 5 ZLVC 4 3 2 1 ZLVC 0 The TP and ZLVC fields are defined on pages 7-3 and 7-4. Execution If cond 1 AND cond 2 AND ...
ROL Rotate Accumulator Left Syntax ROL Operands None 15 1 Opcode 14 0 13 1 12 1 11 1 10 1 Execution Increment PC, then ... C → ACC(0) (ACC(31)) → C (ACC(30:0)) → ACC(31:1) Status Bits Affects C 9 1 8 0 7 0 6 0 5 0 4 0 3 1 2 1 1 0 0 0 This instruction is not affected by SXM. Description The ROL instruction rotates the accumulator left one bit. The value of the carry bit is shifted into the LSB, then the MSB is shifted into the carry bit.
ROR Rotate Accumulator Right Syntax ROR Operands None 15 1 Opcode 14 0 13 1 12 1 11 1 10 1 Execution Increment PC, then ... C → ACC(31) (ACC(0)) → C (ACC(31:1)) → ACC(30:0) Status Bits Affects C 9 1 8 0 7 0 6 0 5 0 4 0 3 1 2 1 1 0 0 1 This instruction is not affected by SXM. Description The ROR instruction rotates the accumulator right one bit. The value of the carry bit is shifted into the MSB of the accumulator, then the LSB of the accumulator is shifted into the carry bit.
RPT Repeat Next Instruction Syntax RPT dma RPT ind [, ARn] RPT #k Operands dma: n: k: ind: Direct addressing Indirect addressing Short immediate 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register 8-bit short immediate value Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– RPT dma Opcode 15 14 13 12 11 10 9 8 7 0 0 0 0 1 0 1 1 0 6 5 4 3 2 1 0 1 0 dma RPT ind [, ARn] 15 14 13 12 11 10 9 8 7 0 0 0 0
Repeat Next Instruction Cycles RPT Cycles for a Single RPT Instruction (Using Direct and Indirect Addressing) Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 2† 1+p External 1+d 1+d 1+d 2+d+p † If the operand and the code are in the same SARAM block Cycles for a Single RPT Instruction (Using Short Immediate Addressing) Example 1 ROM DARAM SARAM External 1 1 1 1+p RPT DAT127 ;(DP = 31: addresses 0F80h–0FFFh) ;Repeat next instruction 13 times.
SACH Store High Accumulator With Shift Syntax SACH dma [, shift2 ] SACH ind [, shift2 [, ARn] ] Operands dma: shift2: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Left shift value from 0 to 7 (defaults to 0) Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– SACH dma [ , shift2 ] Opcode 15 14 13 12 11 1 0 0 1 1 10 9 8 shift2 7 6 5 4 0 3 2 1 0 1 0 dma SACH ind [ ,
SACH Store High Accumulator With Shift Cycles for a Repeat (RPT) Execution of an SACH Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+2† n+p External 2n+nd 2n+nd 2n+nd 2n+2+nd+p † If the operand and the code are in the same SARAM block Example 1 SACH DAT10,1 ;(DP = 4: addresses 0200h–027Fh, ;left shift of 1) Before Instruction ACC X C 4208001h Data Memory 20Ah Example 2 SACH 0h *+,0,AR2 After Instruction ACC X C 4208001h Data Memory 2
SACL Store Low Accumulator With Shift Syntax SACL dma [, shift2 ] SACL ind [, shift2 [, ARn] ] Operands dma: shift2: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Left shift value from 0 to 7 (defaults to 0) Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– SACL dma [ , shift2 ] Opcode 15 14 13 12 11 1 0 0 1 0 10 9 8 shift2 7 6 5 4 0 3 2 1 0 1 0 dma SACL ind [ ,
Store Low Accumulator With Shift SACL Cycles for a Repeat (RPT) Execution of an SACL Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+2† n+p External 2n+nd 2n+nd 2n+nd 2n+2+nd+p † If the operand and the code are in the same SARAM block.
SAR Store Auxiliary Register Syntax SAR ARx, dma SAR ARx, ind [, ARn] Operands dma: x: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the auxiliary register value to be stored Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– n: ind: SAR ARx, dma Opcode 15 14 13 12 11 1 0 0 0 0 10 9 8 x 7 6 5 4 0 3 2 1 0 2 1 0 dma SAR ARx, ind [, ARn] 15 1
Store Auxiliary Register SAR Cycles for a Repeat (RPT) Execution of an SAR Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+2† n+p External 2n+nd 2n+nd 2n+nd 2n+2+nd+p † If the operand and the code are in the same SARAM block Example 1 SAR AR0,DAT30 ;(DP = 6: addresses 0300h–037Fh) Before Instruction Example 2 SAR After Instruction AR0 37h AR0 37h Data Memory 31Eh 18h Data Memory 31Eh 37h AR0,*+ Before Instruction After Instruction AR
SBRK Subtract Short-Immediate Value From Auxiliary Register Syntax SBRK #k Operands k: 8-bit positive short immediate value SBRK #k Opcode Execution Short immediate addressing 15 14 13 12 11 10 9 8 0 1 1 1 1 1 0 0 7 6 5 4 3 2 1 0 k Increment PC, then ... (current AR) – k → current AR Note that k is an 8-bit positive constant.
Set Control Bit Syntax SETC control bit Operands control bit: Opcode SETC C 15 1 14 0 SETC Select one of the following control bits: C Carry bit of status register ST1 CNF RAM configuration control bit of status register ST1 INTM Interrupt mode bit of status register ST0 OVM Overflow mode bit of status register ST0 SXM Sign-extension mode bit of status register ST1 TC Test/control flag bit of status register ST1 XF XF pin status bit of status register ST1 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1
SETC Set Control Bit Words 1 Cycles Cycles for a Single SETC Instruction ROM DARAM SARAM External 1 1 1 1+p Cycles for a Repeat (RPT) Execution of an SETC Instruction Example ROM DARAM SARAM External n n n n+p SETC TC ;TC is bit 11 of ST1 Before Instruction ST1 7-156 x1xxh After Instruction ST1 x9xxh
Shift Accumulator Left Syntax SFL Operands None 15 1 Opcode 14 0 13 1 12 1 11 1 10 1 Execution Increment PC, then ... (ACC(31)) → C (ACC(30:0)) → ACC(31:1) 0 → ACC(0) Status Bits Affects C 9 1 8 0 7 0 6 0 5 0 4 0 3 1 2 0 1 0 SFL 0 1 This instruction is not affected by SXM. Description The SFL instruction shifts the entire accumulator left one bit. The least significant bit is filled with a 0, and the most significant bit is shifted into the carry bit (C).
SFR Shift Accumulator Right Syntax SFR Operands None 15 1 Opcode Execution 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 0 5 0 4 0 3 1 2 0 1 1 0 0 Increment PC, then ... If SXM = 0 Then 0 → ACC(31). If SXM = 1 Then (ACC(31)) → ACC(31) (ACC(31:1)) → ACC(30:0) (ACC(0)) → C Status Bits Affected by SXM Description The SFR instruction shifts the accumulator right one bit. Words Affects C If SXM = 1, the instruction produces an arithmetic right shift.
Shift Accumulator Right Example 1 SFR ;(SXM = 0: no sign extension) Before Instruction ACC Example 2 SFR SFR X C B0001234h After Instruction ACC 0 C ACC 0 C 5800091Ah ;(SXM = 1: sign extend) Before Instruction ACC X C B0001234h After Instruction Assembly Language Instructions D800091Ah 7-159
SPAC Subtract PREG From Accumulator Syntax SPAC Operands None 15 1 Opcode 14 0 13 1 12 1 11 1 10 1 9 1 Execution Increment PC, then ... (ACC) – shifted (PREG) → ACC Status Bits Affected by PM and OVM 8 0 7 0 6 0 5 0 4 0 3 0 2 1 1 0 0 1 Affects C and OV This instruction is not affected by SXM. Description The content of PREG, shifted as defined by the PM status bits, is subtracted from the content of the accumulator. The result is stored in the accumulator.
Store High PREG Syntax SPH dma SPH ind [, ARn] Operands dma: n: ind: SPH Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– SPH dma Opcode 15 14 13 12 11 10 9 8 7 1 0 0 0 1 1 0 1 0 6 5 4 3 2 1 0 2 1 0 dma SPH ind [, ARn] 15 14 13 12 11 10 9 8 7 1 0 0 0 1 1 0 1 1 Note: 6 5 ARU 4 3 N NAR ARU, N, and
SPH Store High PREG Cycles for a Repeat (RPT) Execution of an SPH Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+2† n+p External 2n+nd 2n+nd 2n+nd 2n+2+nd+p † If the operand and the code are in the same SARAM block Example 1 SPH DAT3 ;(DP = 4: addresses 0200h–027Fh, ;PM = 0: no shift) Before Instruction PREG Data Memory 203h Example 2 SPH *,AR7 FE079844h 4567h After Instruction PREG Data Memory 203h AR6 PREG Data Memory 203h 7-162 FE07h
SPL Store Low PREG Syntax SPL dma SPL ind [, ARn] Operands dma: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– SPL dma Opcode 15 14 13 12 11 10 9 8 7 1 0 0 0 1 1 0 0 0 6 5 4 3 2 1 0 2 1 0 dma SPL ind [, ARn] 15 14 13 12 11 10 9 8 7 1 0 0 0 1 1 0 0 1 Note: 6 5 ARU 4 3 N NAR ARU, N, and N
SPL Store Low PREG Cycles for a Repeat (RPT) Execution of an SPL Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+2† n+p External 2n+nd 2n+nd 2n+nd 2n+2+nd+p † If the operand and the code are in the same SARAM block Example 1 SPL DAT5 ;(DP = 4: addresses 0200h–027Fh, ;PM = 2: left shift of four) Before Instruction PREG Data Memory 205h Example 2 SPL *,AR3 0FE079844h 4567h After Instruction PREG Data Memory 205h AR2 PREG Data Memory 205h 7-1
SPLK Store Long-Immediate Value to Data Memory Syntax SPLK #lk, dma SPLK #lk, ind [, ARn] Operands dma: n: lk: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register 16-bit long immediate value Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– SPLK #lk, dma Opcode 15 14 13 12 11 10 9 8 7 1 0 1 0 1 1 1 0 0 6 5 4 3 2 1 0 2 1 0 dma lk SPLK #lk, ind [, ARn] 15 14 13 12
SPLK Store Long-Immediate Value to Data Memory Example 2 SPLK #1111h,*+,AR4 Before Instruction 7-166 After Instruction ARP 0 ARP 4 AR0 300h AR0 301h Data Memory 300h 07h Data Memory 300h 1111h
Set PREG Output Shift Mode Syntax SPM constant Operands constant: 15 1 Opcode 14 0 SPM Value from 0 to 3 that determines the product shift mode 13 1 12 1 11 1 10 1 9 1 8 1 7 0 Execution Increment PC, then ... constant → product shift mode (PM) bits Status Bits Affects PM 6 0 5 0 4 0 3 0 2 0 1 0 constant This instruction is not affected by SXM.
SQRA Square Value and Accumulate Previous Product Syntax SQRA dma SQRA ind [, ARn] Operands dma: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– SQRA dma Opcode 15 14 13 12 11 10 9 8 7 0 1 0 1 0 0 1 0 0 6 5 4 3 2 1 0 2 1 0 dma SQRA ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 0 1 0 0 1 0 1 5 4 ARU
Square Value and Accumulate Previous Product SQRA Cycles for a Repeat (RPT) Execution of an SQRA Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+p+nd † If the operand and the code are in the same SARAM block Example 1 SQRA DAT30 ;(DP = 6: addresses 0300h–037Fh, ;PM = 0: no shift of product) Before Instruction Data Memory 31Eh 0Fh After Instruction Data Memory 31Eh 0Fh TREG 3h TREG 0Fh PREG 12Ch PREG
SQRS Square Value and Subtract Previous Product Syntax SQRS dma SQRS ind [, ARn] Operands dma: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– SQRS dma Opcode 15 14 13 12 11 10 9 8 7 0 1 0 1 0 0 1 1 0 6 5 4 3 2 1 0 2 1 0 dma SQRS ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 0 1 0 0 1 1 1 5 4 ARU 3
Square Value and Subtract Previous Product SQRS Cycles for a Repeat (RPT) Execution of an SQRS Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+p+nd † If the operand and the code are in the same SARAM block Example 1 SQRS DAT9 ;(DP = 6: addresses 0300h–037Fh, ;PM = 0: no shift of product) Before Instruction Data Memory 309h SQRS 08h TREG 1124h TREG 08h PREG 190h PREG 40h X C 1450h ACC *,AR5 ;(PM =
SST Store Status Register Syntax SST #m, dma SST #m, ind [, ARn] Operands dma: n: m: 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following: 0 Indicates that ST0 will be stored 1 Indicates that ST1 will be stored Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– ind: Opcode Direct addressing Indirect addressing SST #0, dma 15 14 13 12 11 10 9 8 7 1 0 0 0 1 1 1 0 0 6 5 4 3 2 1 0 2 1 0 dma
SST Store Status Register Status registers ST0 and ST1 are defined in Section 3.5, Status Registers ST0 and ST1, on page 3-15.
SUB Subtract From Accumulator Syntax SUB dma [, shift ] SUB dma,16 SUB ind [,shift [, ARn] ] SUB ind,16[ , ARn] SUB #k SUB #lk [,shift ] Operands dma: shift: n: k: lk: ind: Opcode Direct addressing Direct with left shift of 16 Indirect addressing Indirect with left shift of 16 Short immediate Long immediate 7 LSBs of the data-memory address Left shift value from 0 to 15 (defaults to 0) Value from 0 to 7 designating the next auxiliary register 8-bit short immediate value 16-bit long immediate value Sel
Subtract From Accumulator Execution Increment PC, then ...
SUB Subtract From Accumulator Cycles Cycles for a Single SUB Instruction (Using Direct and Indirect Addressing) Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 2† 1+p External 1+d 1+d 1+d 2+d+p † If the operand and the code are in the same SARAM block.
Subtract From Accumulator Before Instruction SUB After Instruction ARP 7 ARP 0 AR7 301h AR7 300h Data Memory 301h 04h Data Memory 301h 04h 09h ACC ACC Example 3 X C #8h 1 C SUB X C 07h #0FFFh,4 After Instruction ACC 0 C X C FFFFFFFFh ;(Left shift by four, SXM = 0) Before Instruction ACC 01h ;(SXM = 1: sign-extension mode) Before Instruction ACC Example 4 SUB 0FFFFh After Instruction ACC 1 C Assembly Language Instructions 0Fh 7-177
SUBB Subtract From Accumulator With Borrow Syntax SUBB dma SUBB ind [, ARn] Operands dma: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– SUBB dma Opcode 15 14 13 12 11 10 9 8 7 0 1 1 0 0 1 0 0 0 6 5 4 3 2 1 0 1 0 dma SUBB ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 1 0 0 1 0 0 1 Note: 6 5 4 ARU
Subtract From Accumulator With Borrow SUBB Cycles for a Repeat (RPT) Execution of an SUBB Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+p+nd † If the operand and the code are in the same SARAM block Example 1 SUBB DAT5 ;(DP = 8: addresses 0400h–047Fh) Before Instruction Data Memory 405h ACC Example 2 SUBB 0 C After Instruction 06h Data Memory 405h 06h ACC 06h 0 C 0FFFFFFFFh * Before Instruction Af
SUBC Conditional Subtract Syntax SUBC dma SUBC ind [, ARn] Operands dma: n: ind: Opcode Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– SUBC dma 15 14 13 12 11 10 9 8 7 0 0 0 0 1 0 1 0 0 6 5 4 3 2 1 0 2 1 0 dma SUBC ind [, ARn] 15 14 13 12 11 10 9 8 7 0 0 0 0 1 0 1 0 1 Note: Execution 6 5 ARU 4 3 N
Conditional Subtract SUBC SUBC affects OV but is not affected by OVM; therefore, the accumulator does not saturate upon positive or negative overflows when executing this instruction. The carry bit is affected in the normal manner during this instruction: the carry bit is cleared (C = 0) if the result of the subtraction generates a borrow and is set (C = 1) if it does not generate a borrow.
SUBS Subtract From Accumulator With Sign Extension Suppressed Syntax SUBS dma SUBS ind [, ARn] Operands dma: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– SUBS dma Opcode 15 14 13 12 11 10 9 8 7 0 1 1 0 0 1 1 0 0 6 5 4 3 2 1 0 2 1 0 dma SUBS ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 1 0 0 1 1 0 1
Subtract From Accumulator With Sign Extension Suppressed SUBS Cycles for a Repeat (RPT) Execution of an SUBS Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+p+nd † If the operand and the code are in the same SARAM block Example 1 SUBS DAT2 ;(DP = 16, SXM = 1) Before Instruction Data Memory 802h ACC Example 2 SUBS X C * After Instruction 0F003h Data Memory 802h 0F105h ACC 0F003h 1 C 102h ;(SXM = 1) B
SUBT Subtract From Accumulator With Shift Specified by TREG Syntax SUBT dma SUBT ind [, ARn] Operands dma: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– SUBT dma Opcode 15 14 13 12 11 10 9 8 7 0 1 1 0 0 1 1 1 0 6 5 4 3 2 1 0 1 0 dma SUBT ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 1 0 0 1 1 1 1 Not
Subtract From Accumulator With Shift Specified by TREG Cycles SUBT Cycles for a Single SUBT Instruction Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 2† 1+p External 1+d 1+d 1+d 2+d+p † If the operand and the code are in the same SARAM block.
TBLR Table Read Syntax TBLR dma TBLR ind [, ARn] Operands dma: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– TBLR dma Opcode 15 14 13 12 11 10 9 8 7 1 0 1 0 0 1 1 0 0 6 5 4 3 2 1 0 2 1 0 dma TBLR ind [, ARn] 15 14 13 12 11 10 9 8 7 1 0 1 0 0 1 1 0 1 Note: Execution 6 5 4 ARU 3 N NAR
Table Read TBLR Cycles Cycles for a Single TBLR Instruction Program Operand ROM DARAM SARAM External Source: DARAM/ROM Destination: DARAM 3 3 3 3+pcode Source: SARAM Destination: DARAM 3 3 3 3+pcode Source: External Destination: DARAM 3+psrc 3+psrc 3+psrc 3+psrc +pcode Source: DARAM/ROM Destination: SARAM 3 3 3 4† 3+pcode Source: SARAM Destination: SARAM 3 3 3 4† 3+pcode Source: External Destination: SARAM 3+psrc 3+psrc 3+psrc 4+psrc † 3+psrc +pcode Source: DARAM/ROM Des
TBLR Table Read Cycles for a Repeat (RPT) Execution of a TBLR Instruction (Continued) Program Operand ROM DARAM SARAM External Source: DARAM/ROM Destination: SARAM n+2 n+2 n+2 n+4† n+2+pcode Source: SARAM Destination: SARAM n+2 2n‡ n+2 2n‡ n+2 2n‡ 2n+2§ n+2+pcode 2n‡ Source: External Destination: SARAM n+2+npsrc n+2+npsrc n+2+npsrc n+4+npsrc † n+2+npsrc +pcode Source: DARAM/ROM Destination: External 2n+2+nddst 2n+2+nddst 2n+2+nddst 2n+4+nddst +pcode Source: SARAM Destination: Exte
Table Write Syntax TBLW dma TBLW ind [, ARn] Operands dma: n: ind: TBLW Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– TBLW dma Opcode 15 14 13 12 11 10 9 8 7 1 0 1 0 0 1 1 1 0 6 5 4 3 2 1 0 2 1 0 dma TBLW ind [, ARn] 15 14 13 12 11 10 9 8 7 1 0 1 0 0 1 1 1 1 Note: Execution 6 5 4 ARU 3 N NAR
TBLW Table Write Cycles Cycles for a Single TBLW Instruction Program Operand ROM DARAM SARAM External Source: DARAM/ROM Destination: DARAM 3 3 3 3+pcode Source: SARAM Destination: DARAM 3 3 3 3+pcode Source: External Destination: DARAM 3+dsrc 3+dsrc 3+dsrc 3+dsrc +pcode Source: DARAM/ROM Destination: SARAM 3 3 3 4† 3+pcode Source: SARAM Destination: SARAM 3 3 3 4† 3+pcode Source: External Destination: SARAM 3+dsrc 3+dsrc 3+dsrc 4+dsrc † 3+dsrc +pcode Source: DARAM/ROM Dest
Table Write TBLW Cycles for a Repeat (RPT) Execution of a TBLW Instruction (Continued) Program Operand ROM DARAM SARAM External Source: DARAM/ROM Destination: SARAM n+2 n+2 n+2 n+3† n+2+pcode Source: SARAM Destination: SARAM n+2 2n‡ n+2 2n‡ n+2 2n‡ 2n+1§ n+2+pcode 2n‡ Source: External Destination: SARAM n+2+ndsrc n+2+ndsrc n+2+ndsrc n+3+ndsrc † n+2+ndsrc +pcode Source: DARAM/ROM Destination: External 2n+2+npdst 2n+2+npdst 2n+2+npdst 2n+3+npdst +pcode Source: SARAM Destination: Ext
TRAP Software Interrupt Syntax TRAP Operands None 15 1 Opcode 14 0 13 1 12 1 11 1 10 1 9 1 8 0 7 0 6 1 5 0 4 1 3 0 2 0 1 0 0 1 Execution (PC) + 1 → stack 22h → PC Status Bits Not affected by INTM; does not affect INTM. Description The TRAP instruction is a software interrupt that transfers program control to program-memory location 22h and pushes the program counter (PC) plus 1 onto the hardware stack.
XOR Exclusive OR With Accumulator Syntax XOR dma XOR ind [, ARn] XOR #lk, [, shift ] XOR #lk,16 Operands dma: shift: n: lk: ind: Opcode Direct addressing Indirect addressing Long immediate addressing Long immediate with left shift of 16 7 LSBs of the data-memory address Left shift value from 0 to 15 (defaults to 0) Value from 0 to 7 designating the next auxiliary register 16-bit long immediate value Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– XOR dma 15 14 13 12 11 1
XOR Exclusive OR With Accumulator Status Bits None Description With direct or indirect addressing, the low half of the accumulator value is exclusive ORed with the content of the addressed data memory location, and the result replaces the low half of the accumulator value; the upper half of the accumulator value is unaffected. With immediate addressing, the long immediate constant is shifted and zero filled on both ends and exclusive ORed with the entire content of the accumulator.
Exclusive OR With Accumulator Example 1 XOR DAT127 ;(DP = 511: addresses FF80h–FFFFh) Before Instruction Data Memory 0FFFFh ACC Example 2 XOR 0F0F0h X C 12345678h After Instruction Data Memory 0FFFFh ACC 0F0F0h X C ARP 7 AR7 300h Data Memory 300h ACC XOR 1234A688h *+,AR0 Before Instruction Example 3 XOR 0FFFFh X C #0F0F0h,4 1234F0F0h After Instruction ARP 0 AR7 301h Data Memory 300h ACC 0FFFFh X C ;(First shift data value left by ;four) Before Instruction ACC X C 12340F0Fh
ZALR Zero Low Accumulator and Load High Accumulator With Rounding Syntax ZALR dma ZALR ind [, ARn] Operands dma: n: ind: Direct addressing Indirect addressing 7 LSBs of the data-memory address Value from 0 to 7 designating the next auxiliary register Select one of the following seven options: * *+ *– *0+ *0– *BR0+ *BR0– ZALR dma Opcode 15 14 13 12 11 10 9 8 7 0 1 1 0 1 0 0 0 0 6 5 4 3 2 1 0 2 1 0 dma ZALR ind [, ARn] 15 14 13 12 11 10 9 8 7 0 1 1 0 1 0 0
ZALR Zero Low Accumulator and Load High Accumulator With Rounding Cycles for a Repeat (RPT) Execution of a ZALR Instruction Program Operand ROM DARAM SARAM External DARAM n n n n+p SARAM n n n, n+1† n+p External n+nd n+nd n+nd n+1+p+nd † If the operand and the code are in the same SARAM block Example 1 ZALR DAT3 ;(DP = 32: addresses 1000h–107Fh) Before Instruction Data Memory 1003h ACC Example 2 ZALR 3F01h X C 77FFFFh After Instruction Data Memory 1003h ACC 3F01h X C 3F0180
Chapter 8 On-Chip Peripherals This chapter discusses on-chip peripherals connected to the ’C2xx CPU and their control registers. The on-chip peripherals are controlled through memory-mapped registers. The operations of the timer and the serial ports are synchronized to the processor through interrupts and interrupt polling.
Control of On-Chip Peripherals 8.1 Control of On-Chip Peripherals The on-chip peripherals are controlled by accessing control registers that are mapped to on-chip I/O space. Data is also transferred to and from the peripherals through these registers. Setting and clearing bits in these registers can enable, disable, initialize, and dynamically reconfigure the on-chip peripherals. On a device reset, the CPU sends an internal SRESET signal to the peripheral circuits.
Control of On-Chip Peripherals Table 8–1. Peripheral Register Locations and Reset Conditions (Continued) Register Name I/O Address ’C209 Other ’C2xx Reset Value Effects at Reset IOSR – FFF6h 18xxh I/O status register. Auto-baud alignment is disabled. Error and status flags are reset. The lower eight bits are dependent on the values on pins IO0, IO1, IO2, and IO3 at reset. BRD – FFF7h 0001h Baud rate divisor register. A baud rate of (CLKOUT1 rate)/16 is selected.
Clock Generator 8.2 Clock Generator The high pulse of the master clock output signal (CLKOUT1) signifies the logic phase of the device (the phase when values are changed), while the low pulse signifies the latch phase (the phase when values are latched). CLKOUT1 determines much of the device’s operational speed. For example: - The timer clock rate is a fraction of the rate of CLKOUT1. Each instruction cycle is equal to one CLKOUT1 period.
Clock Generator - External Oscillator. CLKIN is the output of an external oscillator, which is connected to the CLKIN/X2 pin. The X1 pin must be left unconnected. See Figure 8–2. Figure 8–2. Using an External Oscillator ’C2xx No connection Oscillator X1 CLKIN/X2 Regardless of the method used to generate CLKOUT1, CLKOUT1 is also available at the CLKOUT1 pin, unless the pin is turned off by the CLK register (see Section 8.3).
Clock Generator ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Table 8–2.
CLKOUT1-Pin Control (CLK) Register 8.3 CLKOUT1-Pin Control (CLK) Register You can use bit 0 of the CLK register to turn off the pin for the master clock output signal (CLKOUT1). The CLK register is located at address FFE8h in I/O space and has the organization shown in Figure 8–3. Figure 8–3.
Timer 8.4 Timer The ’C2xx features an on-chip timer with a 4-bit prescaler. This timer is a down counter that can be stopped, restarted, reset, or disabled by specific status bits. You can use the timer to generate periodic CPU interrupts. Figure 8–4 shows a functional block diagram of the timer. There is a 16-bit main counter (TIM) and a 4-bit prescaler counter (PSC). The TIM is reloaded from the period register PRD. The PSC is reloaded from the period register TDDR. Figure 8–4.
Timer The TINT request automatically sets the TINT flag bit in the interrupt flag register (IFR). You can mask or unmask the request with the interrupt mask register (IMR). If you are not using the timer, mask TINT so that it does not cause an unexpected interrupt. 8.4.1 Timer Operation Here is a typical sequence of events for the timer: 1) The PSC decrements on each succeeding CLKOUT1 pulse until it reaches 0.
Timer sor v are the TIM and PRD, respectively. Both are16-bit registers mapped to I/O space. The 4-bit TDDR (timer divide-down register) and the 4-bit PSC (prescaler counter) are contained in the timer control register (TCR) described in subsection 8.4.2. The TIM (timer counter register) and the PRD (timer period register) are 16-bit registers described in subsection 8.4.3. You can read the TCR, TIM, and PRD to obtain the current status of the timer and its counters.
Timer Figure 8–5. ’C2xx Timer Control Register (TCR) — I/O-Space Address FFF8h ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ 15 Note: 12 11 10 Reserved FREE SOFT 0 R/W–0 R/W–0 9 6 5 4 3 0 PSC TRB TSS TDDR R/W–0 R/W–0 W–0 R/W–0 0 = Always read as zeros; R = Read access; W = Write access; value following dash (–) is value after reset. Bits 15–12 Reserved. Bits 15–12 are reserved and are always read as 0s.
Timer Bit 4 TSS — Timer stop status bit. TSS stops or starts the timer. At reset, TSS is cleared to 0 and the timer immediately starts. Bits 3–0 8.4.3 TSS = 0 Starts or restarts the timer. TSS = 1 Stops the timer. TDDR — Timer divide-down register. Every (TDDR + 1) CLKOUT1 cycles, the timer counter register (TIM) decrements by one. At reset, the TDDR bits are cleared to 0. If you want to increase the overall timer count by an integer factor, write this factor minus one to the four TDDR bits.
Timer 8.4.4 Setting the Timer Interrupt Rate When the divide-down value (TDDR) is 0, you can program the timer to generate an interrupt (TINT) every 2 to 65 536 cycles by programming the period register (PRD) from 0 to 65 535 (FFFFh). When TDDR is nonzero (1 to 15), the timer interrupt rate decreases. If TDDR, PRD, or both are nonzero, the timer interrupt rate is given by: TINT rate + ) CLKOUT1 rate (TDDR 1) (PRD ) 1) Note: When TDDR = PRD = 0, the timer interrupt rate defaults (CLKOUT1 rate)/2.
Wait-State Generator 8.5 Wait-State Generator Wait states are necessary when you want to interface the ’C2xx with slower external logic and memory. By adding wait states, you lengthen the time the CPU waits for external memory or an external I/O port to respond when the CPU reads from or writes to that memory or port. Specifically, the CPU waits one extra cycle (one CLKOUT1 cycle) for every wait state. The wait states operate on CLKOUT1 cycle boundaries.
Wait-State Generator state generator, see subsection 11.4.3 on page 11-16. To avoid bus conflicts, all writes to external addresses take at least two cycles. Figure 8–6. ’C2xx Wait-State Generator Control Register (WSGR) — I/O-Space Address FFFCh ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ 15 Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Reserved ISWS DSWS PSUWS PSLWS 0 R/W–111 R/W–111 R/W–111 R/W–111 0 0 = Always read as zeros; R = Read access; W = Write access; value following dash (–) is value after reset.
Wait-State Generator Table 8–4 shows how to set the number of wait states you want for each type of off-chip memory. For example, if you write 1s to bits 0 through 5, the device will generate seven wait states for off-chip lower program memory and seven wait states for off-chip upper program memory. Table 8–4.
General-Purpose I/O Pins 8.6 General-Purpose I/O Pins The ’C2xx provides pins that can be used to supply input signals from an external device or output signals to an external device. These pins are not bound to specific uses; rather, they can provide input or output signals for a great variety purposes. You have access to the general-purpose input pin BIO and the general-purpose output pin XF.
General-Purpose I/O Pins Figure 8–7. BIO Timing Diagram Example CLKOUT1 1 CLKOUT1 cycle BIO 8.6.2 Output Pin XF The XF pin is the external flag output pin. If you connect XF to an input pin of another processor, you can use XF as a signal to other processor. The most recent XF value is latched in the ’C2xx, and that value is indicated by the XF status bit of status register ST1.
Chapter 9 Synchronous Serial Port The ’C2xx devices have a synchronous serial port that provides direct communication with serial devices such as codecs (coder/decoders) and serial A/D converters. The serial port may also be used for intercommunication between processors in multiprocessing applications.
Overview of the Synchronous Serial Port 9.1 Overview of the Synchronous Serial Port Both receive and transmit operations of the synchronous serial port have a four-word-deep first-in, first-out (FIFO) buffer. The FIFO buffers reduce the amount of CPU overhead inherent in servicing transmit or receive data by reducing the number of transmit or receive interrupts that occur during a transfer.
Components and Basic Operation 9.2 Components and Basic Operation The synchronous serial port has several hard-wired parts, including two FIFO buffers and six signal pins. Figure 9–1 shows how the components of the synchronous serial port are interconnected. Figure 9–1.
Components and Basic Operation - Data signal. The data signal carries the actual data that is transferred in the transmit/receive operation. The data signal transmit pin (DX) of one device should be connected to the data signal receive (DR) pin on another device. Table 9–1 describes the six pins that use these signals. Table 9–1. SSP Interface Pins Pin Name Description CLKX Transmit clock input or output.
Components and Basic Operation Figure 9–2. 2-Way Serial Port Transfer With External Frame Sync and External Clock TMS320C203 TLC320AD55C Analog signal A/D Analog signal D/A DOUT DIN SCK DR DX CLKX CLKR FS FSX FSR Legend: DOUT DIN SCK FS 9.2.
Components and Basic Operation 9.2.3 Interrupts The synchronous serial port (SSP) has two hardware interrupts that let the processor know when the FIFO buffers need to be serviced: - Transmit interrupts (XINTs) cause a branch to address 000Ah in program space whenever the transmit-interrupt trigger condition is met. Set the trigger condition by setting bits FT1 and FT0 in the SSPCR (see Table 9–3 on page 9-9). XINTs have a priority level of 8 (1 being highest).
Components and Basic Operation Receiving a word through the serial port typically is done as follows: 1) Data from the DR pin is shifted, bit-by-bit (MSB first), into the receive shift register (RSR). 2) When the RSR is full, the RSR copies the data to the receive FIFO buffer. 3) The process then does one of two things, depending upon the state of the receive FIFO buffer: - If the receive FIFO buffer is not full, the process repeats from step 1.
Controlling and Resetting the Port 9.3 Controlling and Resetting the Port The synchronous serial port control register (SSPCR) controls the operation of the synchronous serial port. To configure the serial port, a total of two writes to the SSPCR are necessary: 1) Write your choices to the configuration bits and place the port in reset by writing zeros to SSPCR bits XRST and RRST. 2) Write your choices to the configuration bits and take the port out of reset by writing ones to bits XRST and RRST.
Controlling and Resetting the Port ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ Table 9–2. Run and Emulation Modes FREE SOFT Run/Emulation Mode 0 0 Immediate stop 0 1 Stop after completion of word 1 0 Free run 1 1 Free run Note: If an option besides immediate stop is chosen for the receiver, an overflow error is possible. The default mode (selected at reset) is immediate stop.
Controlling and Resetting the Port Bits 9–8 FR1, FR0 — FIFO receive-interrupt bits. The values you write to FR0 and FR1 set an interrupt trigger condition based on the contents of the receive FIFO buffer. When this condition is met, a receive interrupt (RINT) is generated and the data can be transferred in from the FIFO buffer using the IN instruction. Table 9–4 lists the possible trigger conditions.
Controlling and Resetting the Port Bit 3 Bit 2 Bit 1 TXM — Transmit mode. This bit determines the source device for the frame synchronization (frame sync) pulse for transmissions. It configures the transmit frame sync pin (FSX) as an output or as in input. Note that the receive frame sync pin (FSR) is always configured as an input. TXM = 0 An external frame sync source is selected. FSX is configured as an input and accepts an external frame sync signal.
Controlling and Resetting the Port Bit 0 DLB — Digital loopback mode. The DLB bit can be used to put the serial port in digital loopback mode. DLB = 0 Digital loopback mode is disabled. The DR, FSR, and CLKR signals are connected to their respective device pins. DLB = 1 Digital loopback mode is enabled. DR and FSR become internally connected to DX and FSX, respectively. The FSX and DX signals appear on the device pins, but FSR and DR do not.
Controlling and Resetting the Port A transmit frame sync pulse marks the start of a data transmission. The synchronous serial port can transmit using the internal frame sync source or using an external source: - To use internal frame sync pulses, set the TXM bit in the SSPCR to 1. To use external frame sync pulses: 1) Connect the frame sync source to the FSX pin of the transmitter and to the FSR pin of the receiver. 2) Set the TXM bit in the SSPCR to 0 to enable external frame syncs.
Controlling and Resetting the Port 1) Create interrupt service routines for XINTs and RINTs and include a branch to each service routine at the appropriate interrupt vector address: - The RINT vector is fetched from address 0008h. The XINT vector is fetched from address 000Ah. 2) Select when you want interrupts to occur and set the FR0, FR1, FT0, and FT1 bits accordingly.
Managing the Contents of the FIFO Buffers 9.4 Managing the Contents of the FIFO Buffers The SDTR is a read/write register (at I/O address FFF0h) that is used to send data to the transmit FIFO buffer and to extract data from the receive FIFO buffer. A word is written to the SDTR by the OUT instruction. When the transmit FIFO buffer is full, additional writes to the SDTR are ignored.
Transmitter Operation 9.5 Transmitter Operation Transmitter operation is different in continuous and burst modes. Other differences also depend on whether an internal or an external frame sync is used. 9.5.1 Burst Mode Transmission With Internal Frame Sync (FSM = 1, TXM = 1) Use burst mode transmission with internal frame sync to transfer short packets at rates lower than maximum packet frequency while using an internal frame sync generator.
Transmitter Operation If the SDTR is loaded with a new word while the transmit FIFO buffer is full, the new word will be lost; the FIFO buffer will not accept any more than four words. The burst mode can be discontinued (changed to continuous mode) only by a serial-port or device reset. Changing the FSM bit during transmit or halt will not necessarily cause a switch to continuous mode. Figure 9–4.
Transmitter Operation 9.5.2 Burst Mode Transmission With External Frame Sync (FSM = 1, TXM = 0) Use burst mode transmission with external frame sync to transfer short packets at rates lower than maximum packet frequency while using an external frame sync generator. Place the transmitter in burst mode with external frame sync by setting the FSM bit to 1 and the TXM bit to 0. This mode of operation offers several features: - A frame sync pulse initiates transmission.
Transmitter Operation Figure 9–5. Burst Mode Transmission With External Frame Sync CLKX FSX A15 DX MSB A14 A13 A12 A11 A10 ...
Transmitter Operation 9.5.3 Continuous Mode Transmission With Internal Frame Sync (FSM = 0, TXM = 1) Use continuous mode transmission with internal frame sync to transfer long packets at maximum packet frequency while using an internal frame sync generator. Place the transmitter in continuous mode with internal frame sync by setting the FSM bit to 0 and the TXM bit to 1. In continuous mode, frame sync pulses are not necessary after the initial pulse for consecutive packet transfers.
Transmitter Operation If the SDTR is loaded with a new word while the transmit FIFO buffer is full, the new word will be lost; the FIFO buffer will not accept any more than four words. Continuous mode can be discontinued (changed to burst mode) only by a serial-port or device reset. Changing the FSM bit during transmit or halt will not necessarily cause a switch to burst mode. Figure 9–6. Continuous Mode Transmission With Internal Frame Sync CLKX FSX DX A15 MSB A14 A13 A12 A11 A10 ...
Transmitter Operation 9.5.4 Continuous Mode Transmission with External Frame Sync (FSM=0, TXM=0) Use continuous mode transmission with external frame sync to transfer long packets at maximum packet frequency while using an external frame sync generator. Place the transmitter in continuous mode with external frame sync by setting the FSM bit to 0 and the TXM bit to 0. In continuous mode, frame sync pulses are not necessary after the initial pulse for consecutive packet transfers.
Transmitter Operation The continuous mode can be discontinued (changed to burst mode) only by a serial-port or device reset. Changing the FSM bit during transmit or halt will not necessarily cause a switch to burst mode. Figure 9–7. Continuous Mode Transmission With External Frame Sync CLKX FSX DX A15 MSB A14 A13 A12 A11 A10 ...
Receiver Operation 9.6 Receiver Operation Receiver operation is different in continuous and burst modes. The receiver does not generate frame sync pulses; it always takes the frame sync pulse as an input. In selecting the proper receive mode, note that the mode for the receiver must match the mode for the transmitter. If all four words of the receive FIFO buffer have been filled, the buffer will not accept additional words.
Receiver Operation If a frame sync pulse occurs during reception, reception is restarted, and the bits that were shifted into the RSR before the pulse are lost. Figure 9–8. Burst Mode Reception CLKR FSR DR A15 A14 A13 A12 MSB A11 A10 ... A0 B15 LSB MSB B14 RINT Word loaded to buffer from RSR 9.6.2 Continuous Mode Reception Use continuous mode receive to transfer long packets at maximum packet frequency.
Receiver Operation 3) The remaining bits in the word are then shifted into the RSR, one by one at the falling edge of each consecutive clock cycle. 4) After all bits have been received, if the FIFO buffer is not full, the contents of the RSR are copied to the receive FIFO buffer. If the receive FIFO buffer does become full, an interrupt (RINT) is sent to the CPU, and if overflow has occurred, the overflow (OVF) bit of the SSPCR is set.
Troubleshooting 9.7 Troubleshooting The synchronous serial port uses three bits for troubleshooting and testing. In addition to using these three bits, you must be able to identify special error conditions that may occur in actual transfers. Error conditions result from an unprogrammed event occurring to the serial port. These conditions are operational errors such as overflow, underflow, or a frame sync pulse during a data transfer.
Troubleshooting Table 9–6. Run and Emulation Modes ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ FREE Note: SOFT Run/Emulation Mode 0 0 Immediate stop 0 1 Stop after completion of word 1 0 Free run 1 1 Free run If an option besides immediate stop is chosen for the receiver, an overflow error is possible. The default mode (selected at reset) is immediate stop.
Troubleshooting 9.7.2 Burst Mode Error Conditions The following are descriptions of errors that can occur in burst mode: - 9.7.3 Underflow. Underflow is caused if an external FSX occurs, and there are no new words in the transmit FIFO buffer. Upon receiving the FSX (generally, from an external clock source), transmitter resends the previous word; that is, the value in XSR will be transmitted again. Overflow.
Troubleshooting - - 9-30 Overflow. Overflow occurs when the RSR has new data to pass to the receive FIFO buffer but the FIFO buffer is full. Overflow errors are fatal to a reception. For as long as the FIFO buffer is full, any incoming words will be lost. To restart reception, make space in the buffer by reading from it (through the SDTR). Frame sync pulse during a transmission. After the initial frame sync, no others should occur during transmission.
Chapter 10 Asynchronous Serial Port The ’C2xx has an asynchronous serial port that can be used to transfer data to and from other devices.
Overview of the Asynchronous Serial Port 10.1 Overview of the Asynchronous Serial Port The on-chip asynchronous serial port (ASP) provides easy serial data communication between host CPUs and the ’C2xx or between two ’C2xx devices. The asynchronous mode of data communication is often referred to as UART (universal asynchronous receive and transmit).
Components and Basic Operation 10.2 Components and Basic Operation Figure 10–1 shows the main components of the asynchronous serial port. Figure 10–1. Asynchronous Serial Port Block Diagram Internal data bus Control logic (receive) ADTR ADTR Control logic (transmit) TXRXINT TXRXINT Sequence control RX ARSR CLKOUT1 AXSR Baud-rate generator Sequence control TX 10.2.1 Signals Two types of signals are used in asynchronous serial port (ASP) operations: - - Data signal.
Components and Basic Operation Table 10–1. Asynchronous Serial Port Interface Pins Pin Name Description TX Asynchronous serial port data transmit pin. Transmits serial data from the asynchronous serial port transmit shift register (AXSR). RX Asynchronous serial port data receive pin. Receives serial data into the asynchronous serial port receive shift register (ARSR). IO0 General purpose I/O pin 0. Can be used for general purpose I/O or for handshaking by the UART. IO1 General purpose I/O pin 1.
Components and Basic Operation - - I/O status register (IOSR). Bits in the IOSR indicate detection of the incoming baud rate, various error conditions, the status of data transfers, detection of a break on the RX pin, the status of pins IO3–IO0, and detection of changes on pins IO3–IO0. The IOSR is at address FFF6h in I/O space. For detailed descriptions of the bits in the IOSR, see subsection 10.3.2. Baud-rate divisor register (BRD).
Components and Basic Operation 10.2.5 Basic Operation Figure 10–2 shows a typical serial link between a ’C2xx device and any host CPU. In this mode of communication, any 8-bit character can be transmitted or received serially by way of the transmit data pin (TX) or the receive data pin (RX), respectively. The data transmitted or received through the TX and RX pins will be at TTL level.
Controlling and Resetting the Port 10.3 Controlling and Resetting the Port The asynchronous serial port is programmed through three on-chip registers mapped to I/O space: the asynchronous serial port control register (ASPCR), the I/O status register (IOSR), and the baud-rate divisor register (BRD). This section describes the contents of each of these registers and also explains the use of associated control features. 10.3.
Controlling and Resetting the Port Bits 12–10 Reserved. Always read as 0s. Bit 9 DIM — Delta interrupt mask. DIM selects whether or not delta interrupts are asserted on the TXRXINT interrupt line. A delta interrupt is generated by a change on one of the general-purpose I/O pins (IO3, IO2, IO1, or IO0). Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 10-8 DIM = 0 Disables delta interrupts. DIM = 1 Enables delta interrupts. TIM — Transmit interrupt mask.
Controlling and Resetting the Port Bit 3 Bit 2 Bit 1 Bit 0 CIO3 — Configuration bit for IO3. CIO3 configures I/O pin 3 (IO3) as an input or as an output. CIO3 = 0 IO3 is configured as an input. This is the default value at reset. CIO3 = 1 IO3 is configured as an output. CIO2 — Configuration bit for IO2. CIO2 configures I/O pin 2 (IO2) as an input or as an output. CIO2 = 0 IO2 is configured as an input. This is the default value at reset. CIO2 = 1 IO2 is configured as an output.
Controlling and Resetting the Port 10.3.2 I/O Status Register (IOSR) The IOSR returns the status of the asynchronous serial port and of I/O pins IO0–IO3. The IOSR is a 16-bit, on-chip register mapped to address FFF6h in I/O space. Figure 10–4 shows the fields in the IOSR, and bit descriptions follow the figure.
Controlling and Resetting the Port Bit 11 THRE — Transmit register (ADTR) empty indicator. THRE is set to 1 when the contents of the transmit register (ADTR) are transferred to the transmit shift register (AXSR). THRE is reset to 0 by the loading of the transmit register with a new character. A device reset sets THRE to 1. The emptying of the ADTR also generates an interrupt (TXRXINT). Bit 10 THRE = 0 The transmit register is not empty. Port operation is normal.
Controlling and Resetting the Port Bit 7 DIO3 — Change detect bit for IO3. DIO3 indicates whether a change has occurred on the IO3 pin. A change can be detected only when IO3 is configured as an input by the CIO3 bit of the ASPCR (CIO3 = 0) and the serial port is enabled by the URST bit of the ASPCR (URST = 1). Writing a 1 to DIO3 clears it to 0. The detection of a change on the IO3 pin also generates an interrupt (TXRXINT). Bit 6 DIO3 = 0 No change is detected on IO3.
Controlling and Resetting the Port Bit 3 Bit 2 Bit 1 Bit 0 IO3 — Status bit for IO3. When the IO3 pin is configured as an input (by the CIO3 bit of the ASPCR), this bit reflects the current level on the IO3 pin. IO3 = 0 The IO3 signal is low. IO3 = 1 The IO3 signal is high. IO2 — Status bit for IO2. When the IO2 pin is configured as an input (by the CIO2 bit of the ASPCR), this bit reflects the current level on the IO2 pin. IO2 = 0 The IO2 signal is low. IO2 = 1 The IO2 signal is high.
Controlling and Resetting the Port Table 10–2. Common Baud Rates and the Corresponding BRD Values BRD Value in Hexadecimal Baud Rate CLKOUT1 = 20 MHz (50 ns) CLKOUT1 = 28.57 MHz (35 ns) CLKOUT1 = 40 MHz (25 ns) 1200 0411 05CC 0823 2400 0208 02E6 0411 4800 0104 0173 0208 9600 0082 00B9 0104 19200 0041 005C 0082 10.3.4 Using Automatic Baud-Rate Detection The ASP contains auto-baud detection logic, which allows the ASP to lock to the incoming data rate.
Controlling and Resetting the Port 10.3.5 Using I/O Pins IO3, IO2, IO1, and IO0 Pins IO3, IO2, IO1, and IO0 can be individually configured as inputs or outputs and can be used as handshake control for the asynchronous serial port or as general-purpose I/O pins. They are software-controlled through the asynchronous serial port control register (ASPCR) and the I/O status register (IOSR), as shown in Figure 10–5. Figure 10–5.
Controlling and Resetting the Port When pins IO0–IO3 are configured as inputs When pins IO0–IO3 are configured as inputs, the eight LSBs of the IOSR allow you to monitor these four pins. Each of the IOSR bits 3–0, called IO3, IO2, IO1, and IO0, can be used to read the current logic level (high or low) of the signal at the corresponding pin. Each of the bits 7–4, called DIO3, DIO2, DIO1, and DIO0, is used to track a change from a previous known or unknown signal value at the corresponding pin.
Controlling and Resetting the Port 10.3.6 Using Interrupts The asynchronous serial port interrupt (TXRXINT) can be generated by three types of interrupts: - - Transmit interrupts. A transmit interrupt is generated when the ADTR empties during transmission. This indicates that the port is ready to accept a new transmit character. In addition to generating the interrupt, the port sets the THRE bit of the IOSR to 1. Transmit interrupts can be disabled by the TIM bit of the ASPCR. Receive interrupts.
Controlling and Resetting the Port TXRXINT leads the CPU to interrupt vector location 000Ch in program memory. The branch at that location should lead to an interrupt service routine that identifies the cause of the interrupt and then acts accordingly. TXRXINT has a priority level of 9 (1 being highest). TXRXINT is a maskable interrupt and is controlled by the interrupt mask register (IMR) and interrupt flag register (IFR).
Transmitter Operation 10.4 Transmitter Operation The transmitter consists of an 8-bit transmit register (ADTR) and an 8-bit transmit shift register (AXSR). Data to be transmitted is written to the ADTR, and then the port transfers the data to the AXSR. Data written to the transmit register should be written in right-justified form, with the LSB as the rightmost bit.
Receiver Operation 10.5 Receiver Operation The receiver includes two internal 8-bit registers: the receive register (ADTR) and receive shift register (ARSR). The data received at the RX pin should have the serial form shown in Figure 10–7 (the number of stop bits required depends on the value of the STB bit in the ASPCR). Figure 10–7.
Chapter 11 TMS320C209 All ’C2xx devices use the same central processing unit (CPU), bus structure, and instruction set, but the ’C209 has some notable differences. This chapter compares features on the ’C209 with those on other ’C2xx devices and then provides information specific to the ’C209 in the areas of memory and I/O spaces, interrupts, and on-chip peripherals. Topic Page 11.1 ’C209 Versus Other ’C2xx Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.
’C209 Versus Other ’C2xx Devices 11.1 ’C209 Versus Other ’C2xx Devices This section explains the differences between the ’C209 and other ’C2xx devices and concludes with a table to help you find the other information in this manual that applies to the ’C209. 11.1.
’C209 Versus Other ’C2xx Devices - - Memory and I/O Spaces: J J The I/O addresses of the peripheral registers are different on the ’C209. The ’C209 does not support the ’C2xx HOLD operation. Interrupts: J J J J J J The ’C209 has four maskable interrupt lines, none of them shared. The other devices have six interrupt lines, one shared by the INT2 and INT3 pins. The ’C209 does not have an interrupt control register (ICR) because INT2 and INT3 have their own interrupt lines.
’C209 Versus Other ’C2xx Devices For information about: Interrupts Memory Look here: Main description Chapter 5, Program Control Vector locations Table 11–4 (page 11-10) Flag and mask registers Subsection 11.3.1 (page 11-11) Interrupt acknowledge pin Subsection 11.3.2 (page 11-13) Main description Chapter 4, Memory Address maps Figure 11–1 (page 11-6) Configuration Section 11.
’C209 Memory and I/O Spaces 11.2 ’C209 Memory and I/O Spaces The ’C209 does not have an on-chip boot loader and does not support the ’C2xx HOLD operation. Figure 11–1 shows the ’C209 address map.
’C209 Memory and I/O Spaces Figure 11–1.
’C209 Memory and I/O Spaces Do Not Write to Reserved Addresses To avoid unpredictable operation of the processor, do not write to any addresses labeled Reserved. This includes any data-memory address in the range 0000h–005Fh that is not designated for an on-chip register and any I/O address in the range FF00h–FFFFh that is not designated for an on-chip register.
’C209 Memory and I/O Spaces (4K) are mapped to external data memory. Thus, a total of 8K additional addresses (4K program and 4K data) are available for external memory. DARAM blocks B1 and B2 are fixed, but DARAM block B0 may be mapped to program space or data space, depending on the value of the CNF bit (bit 12 of status register ST1): - When CNF = 0, B0 is mapped to data space and is accessible at data addresses 0200h–02FFh. Note that the addressable external program memory increases by 512 words.
’C209 Memory and I/O Spaces Table 11–2.
’C209 Interrupts 11.3 ’C209 Interrupts Table 11–4 lists the interrupts available on the ’C209 and shows their vector locations. In addition, it shows the priority of each of the hardware interrupts. Note that a device reset can be initiated in either of two ways: by driving the RS pin low or by driving the RS pin high. The K value shown for each interrupt vector location is the operand to be used with the INTR instruction if you want to force a branch to that location.
’C209 Interrupts ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ
’C209 Interrupts Figure 11–2.’C209 Interrupt Flag Register (IFR) — Data-Memory Address 0006h ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 15 Note: 4 3 2 1 0 Reserved TINT INT3 INT2 INT1 0 R/W1C–0 R/W1C–0 R/W1C–0 R/W1C–0 0 = Always read as zeros; R = Read access; W1C = Write 1 to this bit to clear it to 0; value following dash (–) is value after reset. Bits 15–4 Reserved. Bits 15–4 are reserved and are always read as 0s. Bit 3 TINT — Timer interrupt flag.
’C209 Interrupts Figure 11–3.’C209 Interrupt Mask Register (IMR) — Data-Memory Address 0004h ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 15 Note: 4 3 2 1 0 Reserved TINT INT3 INT2 INT1 0 R/W–0 R/W–0 R/W–0 R/W–0 Note: 0 = Always read as zeros; R = Read access; W = Write access; value following dash (–) is value after reset. Bits 15–4 Reserved. Bits 15–4 are reserved and are always read as 0s. Bit 3 TINT — Timer interrupt mask. Mask or unmask the internal timer interrupt, TINT, with this bit.
’C209 On-Chip Peripherals 11.4 ’C209 On-Chip Peripherals The ’C209 has these on-chip peripherals: - Clock generator. The clock generator is fundamentally the same on all ’C2xx devices, including the ’C209. However, the ’C209 is limited to the two clock modes described in subsection 11.4.1. Timer. The timer is also fundamentally the same. The difference here is that the timer control register (TCR) on the ’C209 does not offer bits for configuring timer emulation modes. Subsection 11.4.
’C209 On-Chip Peripherals ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ Table 11–5. ’C209 Input Clock Modes Clock Mode CLKOUT1 Rate CLKMOD Oscillator PLL ÷2 CLKOUT1 = CLKIN ÷ 2 0 Enabled Disabled ×2 CLKOUT1 = CLKIN × 2 1 Disabled Enabled Remember the following points when configuring the clock mode: - The modes cannot be configured dynamically.
’C209 On-Chip Peripherals Bit 4 TSS — Timer stop status bit. TSS is a 1-bit flag that stops or starts the timer. To stop the timer, set TSS to 1. To start or restart the timer, set TSS to 0. At reset, TSS is cleared to 0 and the timer immediately starts. Bits 3–0 TDDR —Timer divide-down register. Every (TDDR + 1) CLKOUT1 cycles, the timer counter register (TIM) decrements by one. At reset, the TDDR bits are cleared to 0.
’C209 On-Chip Peripherals Figure 11–5.’C209 Wait-State Generator Control Register (WSGR) — I/O Address FFFFh ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Note: 15–4 3 2 1 0 Reserved AVIS ISWS DSWS PSWS 0 W–1 W–1 W–1 W–1 0 = Always read as zeros; W = Write access; value following dash (–) is value after reset. Bits 15–4 Reserved. Bits 15–4 are reserved and are always read as 0s. Bit 3 AVIS — Address visibility mode. AVIS = 1 enables the address visibility mode of the device.
Appendix AppendixAA Register Summary For the status and control registers of the ’C2xx devices, this appendix summarizes: - Their addresses Their reset values The functions of their bits Topic Page A.1 Addresses and Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 A.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Addresses and Reset Values A.1 Addresses and Reset Values The following tables list the ’C2xx registers, the addresses at which they can be accessed, and their reset values. Note that the registers mapped to internal I/O space on the ’C209 are at addresses different from those of other ’C2xx devices. In addition, the ’C209 wait-state generator control register has a different reset value because there are only four control bits in the register. Table A–1.
Addresses and Reset Values Table A–3.
Register Descriptions A.2 Register Descriptions The following figures summarize the content of the ’C2xx status and control registers that are divided into fields. (The other registers contain no control bits; they simply hold a single 16-bit value.) Each figure in this section provides information in this way: - The value shown in the register is the value after reset. If the value of a particular bit is not affected by reset or depends on pin levels at reset, that bit will contain an X.
Register Descriptions Status Register ST0 15 14 X 13 X 12 X ARP R/W 11 0 X OV OVM R/W ÉÉÉ ÉÉÉ 10 9 8 7 6 5 4 3 2 1 0 1† 1 X X X X X X X X X INTM R/W DP R/W R/W Data page pointer Selects the current page (0, 1, 2, ..., 511) in data memory Overflow mode 0 Accumulator results overflow normally.
Register Descriptions ’C2xx Interrupt Flag Register (IFR) — Except ’C209 — Data-Memory Address 0006h ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ 15 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Reserved† TXRXINT XINT RINT TINT INT2/INT3 HOLD/INT1 R/W1C R/W1C R/W1C R/W1C Receive interrupt flag 0 Interrupt RINT not pending 1 Interrupt RINT pending Transmit interrupt flag 0 Interrupt XINT not pending 1 Interrupt XINT pending Transmit/receive interrupt flag 0 Interrupt TXRXINT not pending 1 Interrupt TXRXINT pending R/W1C
Register Descriptions Interrupt Mask Register (IMR) — Except ’C209 — Data-Memory Address 0004h ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ 15 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Reserved† TXRXINT XINT RINT TINT INT2/INT3 HOLD/INT1 R/W R/W R/W R/W R/W R/W Receive interrupt mask 0 Interrupt RINT masked 1 Interrupt RINT unmasked HOLD/INT1 mask 0 HOLD/INT1 masked 1 HOLD/INT1 unmasked Transmit interrupt mask 0 Interrupt XINT masked 1 Interrupt XINT unmasked Transmit/receive interrupt mask 0 Interrupt TXRXINT m
Register Descriptions Interrupt Control Register (ICR) — I/O Address FFECh ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ 15 5 4 3 2 1 0 0 0 0 0 0 0 Reserved† MODE FINT3 FINT2 MINT3 MINT2 R/W R/W1C R/W1C R/W INT2 mask 0 INT2 request will not reach CPU. 1 INT2 request will reach CPU. INT3 mask 0 INT3 request will not reach CPU. 1 INT3 request will reach CPU. INT2 flag 0 INT2 not pending 1 INT2 pending INT3 flag 0 INT3 not pending 1 INT3 pending HOLD/INT1 pin mode 0 Double-edge mode.
Register Descriptions Timer Control Register (TCR) — Except ’C209 — I/O Address FFF8h ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ 15 12 11 10 0 0 0 Reserved† FREE SOFT 9 6 5 4 0 0 0 0 PSC TRB TSS TDDR R/W R/W R/W 3 0 W R/W R/W Timer reload bit Write 1 to reload timer counters. Always read as 0 Timer divide-down register Holds next value to be loaded into PSC Timer prescaler counter Holds current prescale count for the timer Timer stop status bit 0 Start or restart timer. 1 Stop timer.
Register Descriptions Wait-State Generator Control Register (WSGR) — Except ’C209— I/O Address FFFCh ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ 15 14 13 12 0 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 Reserved† I/O wait states 0 0 0 0 wait states 0 0 1 1 wait state 0 1 0 2 wait states 0 1 1 3 wait states 1 0 0 4 wait states 1 0 1 5 wait states 1 1 0 6 wait states 1 1 1 7 wait states ISWS DSWS R/W PSUWS R/W Data wait states 0 0 0 0 wait states 0 0 1 1 wait state 0 1 0 2 wait states 0 1 1
Register Descriptions CLK Register — I/O Address FFE8h ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 15 1 0 0 0 Reserved† CLKOUT1 R/W CLKOUT1 pin control 0 CLKOUT1 signal available at CLKOUT1 pin 1 CLKOUT1 signal not available at CLKOUT1 pin † These reserved bits are always read as 0s. Writes have no effect.
Register Descriptions ÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁ Synchronous Serial Port Control Register (SSPCR) — I/O Address FFF1h 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 FREE SOFT TCOMP RFNE FT1 FT0 FR1 FR0 R R/W R R/W R/W Receive FIFO buffer status 0 Receive buffer empty. 1 Receive buffer holds data. R/W R/W R/W Generate RINT when . . . 0 0 Receive buffer not empty.
Register Descriptions ÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÉÉÉÉÉÉÉÉÉÉÉÉ ÁÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÉÉÉÉÉÉÉÉÉÉÉÉ ÁÁÁÁÁ ÁÁÁÁ ÁÁ Asynchronous Serial Port Control Register (ASPCR) — I/O Address FFF5h 15 14 13 12 11 10 9 8 0 0 0 0 0 0 FREE SOFT URST Reserved† DIM TIM R/W R/W R/W R/W R/W Port reset 0 Port in reset 1 Port enabled Transmit interrupt mask 0 Disables transmit interrupts 1 Enables transmit interrupts Emulation/run mode
Register Descriptions ÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÉÉÉÉ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁ ÁÁ ÉÉÉÉ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ Á I/O Status Register (IOSR) — I/O Address FFF6h 15 14 13 12 11 10 9 8 0 0 0 1 1 0 0 0 Reserved† ADC‡ BI‡ TEMT THRE‡ FE‡ OE‡ DR‡ R/W1C R/W1C R R R/W1C R/W1C R Data ready indicator for receiver 0 Receive register empty 1 Character has been completely received.
Appendix AppendixBA TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison This appendix contains a table that compares the TMS320C1x, TMS320C2x, TMS320C2xx, and TMS320C5x instructions alphabetically. Each table entry shows the syntax for the instruction, indicates which devices support the instruction, and describes the operation of the instruction. Section B.1 shows a sample table entry and describes the symbols and abbreviations used in the table.
Using the Instruction Set Comparison Table B.1 Using the Instruction Set Comparison Table To help you read the comparison table, this section provides an example of a table entry and a list of acronyms. B.1.1 An Example of a Table Entry In cases where more than one syntax is used, the first syntax is usually for direct addressing and the second is usually for indirect addressing. Where three or more syntaxes are used, the syntaxes are normally specific to a device.
Using the Instruction Set Comparison Table B.1.2 Symbols and Acronyms Used in the Table The following table lists the instruction set symbols and acronyms used throughout this chapter: Table B–1.
Using the Instruction Set Comparison Table Based on the device, this is how the indirect addressing operand {ind} is interpreted: {ind} ’C1x: ’C2x: ’C2xx: ’C5x: { * | *+ | *– } { * | *+ | *– | *0+| *0– | *BR0+ | *BR0– } { * | *+ | *– | *0+| *0– | *BR0+ | *BR0– } { * | *+ | *– | *0+| *0– | *BR0+ | *BR0– } where the possible options are separated by vertical bars (|).
Enhanced Instructions B.2 Enhanced Instructions An enhanced instruction is a single mnemonic that performs the functions of several similar instructions. For example, the enhanced instruction ADD performs the ADD, ADDH, ADDK, and ADLK functions and replaces any of these other instructions at assembly time. For example, when a program using ADDH is assembled for the ’C2xx or ’C5x, ADDH is replaced by an ADD instruction that performs the same function.
Instruction Set Comparison Table B.3 Instruction Set Comparison Table Syntax ABS 1x 2x 2xx √ √ √ 5x √ Description Absolute Value of Accumulator If the contents of the accumulator are less than zero, replace the contents with the 2s complement of the contents. If the contents are ≥ 0, the accumulator is not affected. √ ADCB Add ACCB to Accumulator With Carry Add the contents of the ACCB and the value of the carry bit to the accumulator.
Instruction Set Comparison Table Syntax 1x ADDK #k 2x 2xx 5x √ √ √ Description Add to Accumulator Short Immediate TMS320C1x devices: Add an 8-bit immediate value to the accumulator. TMS320C2x, TMS320C2xx, and TMS320C5x devices: Add an 8-bit immediate value, right justified, to the accumulator with the result replacing the accumulator contents. The immediate value is treated as an 8-bit positive number; sign extension is suppressed.
Instruction Set Comparison Table Syntax 1x 2x 2xx 5x AND dma √ √ √ √ AND With Accumulator AND {ind} [, next ARP] √ √ √ √ √ √ TMS320C1x and TMS320C2x devices: AND the contents of the addressed data-memory location with the 16 LSBs of the accumulator. The 16 MSBs of the accumulator are ANDed with 0s. AND #lk [, shift] Description TMS320C2xx and TMS320C5x devices: AND the contents of the addressed data-memory location or a 16-bit immediate value with the contents of the accumulator.
Instruction Set Comparison Table Syntax 1x 2x 2xx 5x √ B[D] pma [, {ind} [, next ARP ] ] Description Branch Unconditionally With Optional Delay Modify the current auxiliary register and ARP as specified and pass control to the designated programmemory address. If you specify a delayed branch (BD), the next two instruction words (two 1-word instructions or one 2-word instruction) are fetched and executed before branching.
Instruction Set Comparison Table Syntax BBNZ pma [, {ind} [, next ARP ] ] 1x 2x 2xx 5x √ √ √ Description Branch on Bit ≠ Zero If the TC bit = 1, branch to the specified programmemory address. TMS320C2x devices: Modify the current AR and ARP as specified. TMS320C2xx and TMS320C5x devices: If the –p porting switch is used, modify the current AR and ARP as specified.
Instruction Set Comparison Table Syntax BGEZ pma 1x 2x √ 2xx 5x √ √ Branch if Accumulator ≥ Zero √ If the contents of the accumulator ≥ 0, branch to the specified program-memory address. √ BGEZ pma [, {ind} [, next ARP] ] Description TMS320C2x devices: Modify the current AR and ARP as specified. TMS320C2xx and TMS320C5x devices: Modify the current AR and ARP as specified when the –p porting switch is used.
Instruction Set Comparison Table Syntax 1x 2x 2xx 5x BLDD #lk, dma √ √ Block Move From Data Memory to Data Memory BLDD #lk, {ind} [, next ARP] √ √ BLDD dma, #lk √ √ Copy a block of data memory into data memory. The block of data memory is pointed to by src, and the destination block of data memory is pointed to by dst.
Instruction Set Comparison Table Syntax 1x 2x 2xx 5x BLKD dma1, dma2 √ √ √ Description Block Move From Data Memory to Data Memory BLKD dma1, {ind} [, next ARP] √ √ √ Move a block of words from one location in data memory to another location in data memory. Modify the current AR and ARP as specified. RPT or RPTK must be used with BLKD, in the indirect addressing mode, if more than one word is to be moved.
Instruction Set Comparison Table Syntax 1x BNC pma [, {ind} [, next ARP] ] 2x 2xx 5x √ √ √ Description Branch on No Carry If the C bit = 0, branch to the specified programmemory address. TMS320C2x devices: Modify the current AR and ARP as specified. TMS320C2xx and TMS320C5x devices: Modify the current AR and ARP as specified when the –p porting switch is used. √ BNV pma [, {ind} [, next ARP] ] √ √ Branch if No Overflow If the OV flag is clear, branch to the specified programmemory address.
Instruction Set Comparison Table Syntax BZ BZ pma 1x 2x √ 2xx 5x √ √ √ pma [, {ind} [, next ARP]] Description Branch if Accumulator = Zero If the contents of the accumulator = 0, branch to the specified program-memory address. TMS320C2x, TMS320C2xx and TMS320C5x devices: Modify the current AR and ARP as specified. TMS320C2xx and TMS320C5x devices: To modify the AR and ARP, use the –p porting switch.
Instruction Set Comparison Table Syntax CC 1x 2x 2xx 5x √ pma, cond1 [, cond2 ] [, ...] Description Call Conditionally If the specified conditions are met, control is passed to the pma. Not all combinations of conditions are meaningful. √ CC[D] pma, cond1 [, cond2 ] [, ...] Call Conditionally With Optional Delay If the specified conditions are met, control is passed to the pma. Not all combinations of conditions are meaningful.
Instruction Set Comparison Table Syntax 1x CNFP 2x 2xx 5x √ √ √ Description Configure Block as Program Memory Configure on-chip RAM block B0 as program memory. Block B0 is mapped into program-memory locations 65280h–65535h. TMS320C5x devices: Block B0 is mapped into datamemory locations 65024h–65535h. √ CONF 2-bit constant Configure Block as Program Memory Configure on-chip RAM block B0/B1/B2/B3 as program memory.
Instruction Set Comparison Table Syntax EINT 1x 2x 2xx 5x √ √ √ √ Description Enable Interrupts Enable all interrupts; clear the INTM to 0. Maskable interrupts are enabled immediately after the EINT instruction executes. √ EXAR Exchange ACCB With ACC Exchange the contents of the ACC with the contents of the ACCB. √ FORT 1-bit constant Format Serial Port Registers Load the FO with a 0 or a 1. If FO = 0, the registers are configured to receive/transmit 16-bit words.
Instruction Set Comparison Table Syntax 1x 2x INTR K 2xx 5x √ √ Description Soft Interrupt Transfer program control to the program-memory address specified by K (an integer from 0 to 31). This instruction allows you to use your software to execute any interrupt service routine. The interrupt vector locations are spaced apart by two addresses (0h, 2h, 4h, ... , 3Eh), allowing a two-word branch instruction to be placed at each location.
Instruction Set Comparison Table Syntax 1x 2x 2xx 5x LACT dma √ √ √ LACT {ind} [, next ARP] √ √ √ Description Load Accumulator With Shift Specified by T Register Left shift the contents of the addressed data-memory location by the value specified in the 4 LSBs of the T register; load the result into the accumulator. If a shift is specified, left shift the value before loading it into the accumulator.
Instruction Set Comparison Table Syntax 1x 2x 2xx 5x LDP dma √ √ √ √ Load Data-Memory Page Pointer LDP {ind} [, next ARP] √ √ √ √ √ √ TMS320C1x devices: Load the LSB of the contents of the addressed data-memory location into the DP register. All high-order bits are ignored. DP = 0 defines page 0 (words 0–127), and DP = 1 defines page 1 (words 128–143/255).
Instruction Set Comparison Table Syntax 1x 2x 2xx 5x LST #n, dma √ √ √ Description Load Status Register n LST #n, {ind} [, next ARP] √ √ √ Load the contents of the addressed data-memory location into STn. LST1 dma √ √ √ Load ST1 LST1 {ind} [, next ARP] √ √ √ Load the contents of the addressed data-memory location into ST1.
Instruction Set Comparison Table Syntax 1x 2x 2xx 5x MAC pma, dma √ √ √ Description Multiply and Accumulate MAC pma, {ind} [, next ARP] √ √ √ Multiply a data-memory value by a program-memory value and add the previous product (shifted as specified by the PM status bits) to the accumulator.
Instruction Set Comparison Table Syntax 2x 2xx 5x MPYA dma √ √ √ Multiply and Accumulate Previous Product MPYA {ind} [, next ARP] √ √ √ Multiply the contents of the T register (TMS320C2x/ 2xx) or TREG0 (TMS320C5x) by the contents of the addressed data-memory location; place the result in the P register. Add the previous product (shifted as specified by the PM status bits) to the accumulator.
Instruction Set Comparison Table Syntax 1x 2x 2xx 5x dma √ √ √ √ OR With Accumulator OR {ind} [, next ARP] √ √ √ √ OR #lk [, shift] √ √ TMS320C1x and TMS320C2x devices: OR the 16 LSBs of the accumulator with the contents of the addressed data-memory location. The 16 MSBs of the accumulator are ORed with 0s. OR Description TMS320C2xx and TMS320C5x devices: OR the 16 LSBs of the accumulator or a 16-bit immediate value with the contents of the addressed data-memory location.
Instruction Set Comparison Table Syntax 2x 2xx 5x POPD dma √ √ √ Pop Top of Stack to Data Memory POPD {ind} [, next ARP] √ √ √ Transfer the value on the top of the stack into the addressed data-memory location and then pop the stack one level. PSHD dma √ √ √ Push Data-Memory Value Onto Stack PSHD {ind} [, next ARP] √ √ √ Copy the addressed data-memory location onto the top of the stack. The stack is pushed down one level before the value is copied.
Instruction Set Comparison Table Syntax 1x 2x 2xx 5x √ RETE Description Enable Interrupts and Return From Interrupt Copy the contents of the top of the stack into the PC and pop the stack one level. RETE automatically clears the global interrupt enable bit and pops the shadow registers (stored when the interrupt was taken) back into their corresponding strategic registers. The following registers are shadowed: ACC, ACCB, PREG, ST0, ST1, PMST, ARCR, INDX, TREG0, TREG1, TREG2.
Instruction Set Comparison Table Syntax 1x 2x 2xx 5x RPT dma √ √ √ Description Repeat Next Instruction RPT {ind} [, next ARP] √ √ √ RPT #k √ √ RPT #lk √ √ TMS320C2x devices: Load the 8 LSBs of the addressed value into the RPTC; the instruction following RPT is executed the number of times indicated by RPTC + 1.
Instruction Set Comparison Table Syntax 1x 2x 2xx 5x SACH dma [, shift] √ √ √ √ Store High Accumulator With Shift SACH {ind} [, shift [, next ARP] ] √ √ √ √ Copy the contents of the accumulator into a shifter. Shift the entire contents 0, 1, or 4 bits (TMS320C1x) or from 0 to 7 bits (TMS320C2x/2xx/5x), and then copy the 16 MSBs of the shifted value into the addressed data-memory location. The accumulator is not affected.
Instruction Set Comparison Table Syntax 1x 2x 2xx 5x √ SBBB Description Subtract ACCB From Accumulator With Borrow Subtract the contents of the ACCB and the logical inversion of the carry bit from the accumulator. The result is stored in the accumulator; the accumulator buffer is not affected. Clear the carry bit if the result generates a borrow. SBLK #lk [, shift] √ √ √ Subtract From Accumulator Long Immediate With Shift Subtract the immediate value from the accumulator.
Instruction Set Comparison Table Syntax 1x 2x 2xx √ SHM 5x √ Description Set Hold Mode Set the HM status bit to 1. SMMR dma, #lk √ Store Memory-Mapped Register SMMR {ind}, #lk [, next ARP] √ Store the memory-mapped register value, pointed at by the 7 LSBs of the data-memory address, into the long immediate addressed data-memory location. The 9 MSBs of the data-memory address of the memorymapped register are cleared, regardless of the current value of DP or the upper 9 bits of AR(ARP).
Instruction Set Comparison Table Syntax 1x 2x 2xx 5x SQRA dma √ √ √ Description Square and Accumulate Previous Product SQRA {ind} [, next ARP] √ √ √ Add the contents of the P register (shifted as specified by the PM status bits) to the accumulator. Then load the contents of the addressed data-memory location into the T register (TMS320C2x/2xx) or TREG0 (TMS320C5x), square the value, and store the result in the P register.
Instruction Set Comparison Table Syntax 1x 2x 2xx 5x SUB dma [, shift] √ √ √ √ Description Subtract From Accumulator With Shift SUB {ind} [, shift [, next ARP] ] √ √ √ √ SUB #k √ √ SUB #lk [, shift2 ] √ √ TMS320C1x and TMS320C2x devices: Subtract the contents of the addressed data-memory location from the accumulator. If a shift is specified, left shift the value before subtracting. During shifting, low-order bits are zero filled, and high-order bits are sign extended if SXM = 1.
Instruction Set Comparison Table Syntax 1x 2x 2xx 5x Description SUBT dma √ √ √ SUBT {ind} [, next ARP] √ √ √ Subtract From Accumulator With Shift Specified by T Register Left shift the data-memory value as specified by the 4 LSBs of the T register (TMS320C2x/2xx) or TREG1 (TMS320C5x), and subtract the result from the accumulator. If a shift is specified, left shift the data-memory value before subtracting.
Instruction Set Comparison Table Syntax 1x 2x 2xx 5x XOR dma √ √ √ √ Exclusive-OR With Accumulator XOR {ind} [, next ARP] √ √ √ √ √ √ TMS320C1x and TMS320C2x devices: Exclusive-OR the contents of the addressed data-memory location with 16 LSBs of the accumulator. The MSBs are not affected. XOR #lk [, shift] Description TMS320C2xx and TMS320C5x devices: ExclusiveOR the contents of the addressed data-memory location or a 16-bit immediate value with the accumulator.
Instruction Set Comparison Table Syntax 1x 2x 2xx 5x ZALR dma √ √ √ ZALR {ind} [, next ARP] √ √ √ Description Zero Low Accumulator, Load High Accumulator With Rounding Load the contents of the addressed data-memory location into the 16 MSBs of the accumulator. The value is rounded by 1/2 LSB; that is, the 15 LSBs of the accumulator (0–14) are cleared and bit 15 is set to 1.
Appendix AppendixCA Program Examples This appendix provides: - A brief introduction to the process for generating executable program files. Sample programs for implementing simple routines and using interrupts, I/O pins, the timer, and the serial ports. This appendix is not intended to teach you how to use the software development tools.
About About These These Program Program Examples C.1 About These Program Examples Figure C–1 illustrates the basic process for creating assembly language files and then generating executable files from them: 1) Use the ’C2xx assembler to create: - A command file (c203.cmd in the figure) that defines address ranges according to the architecture of the particular ’C2xx device An assembly language program (test.asm in the figure) 2) Assemble the program.
About These Program Examples The program examples in Section C.2 and Section C.3 consist of code for shared files and task-specific files. Table C–1 describes the shared programs. Shared files contain code that is used by multiple task-specific files. The taskspecific programs are described in Table C–2. Every task-specific file that uses the header files includes them by way of the .copy assembler directive: .copy ”init.h” .copy ”vector.h” The assembler brings together the .h files and .asm file.
About These Program Examples Table C–2. Task-Specific Programs in This Appendix (Continued) Program Functional Description See ... uart.asm Causes the asynchronous serial port to transmit a test message continuously at 1200 baud. Baud rate is 1200 at 50-ns cycle time. Example C–9, page C-13 echo.asm Echoes the character received by the asynchronous serial port at 1200 baud Example C–10, page C-14 autobaud.
Shared Program Code C.2 Shared Program Code Example C–1. Generic Command File (c203.cmd) /* /* /* /* /* /* Title: c203.cmd */ Generic command file for linking TMS320C2xx assembler files */ input files: *.obj files */ output files: *.out file */ Map files: *.
Shared Program Code Example C–2. Header File With I/O Register Declarations (init.h) * File: init.h * * Include file with I/O register declarations * .mmregs .bss dmem,10 .def ini_d, start,codtx ini_d: .usect ”new”,10 .data .word 055aah .word 0aa55h * On–chip register equates * CLKOUT clk1 .set 0ffe8h * INTERRUPT CONTROL icr .set 0ffech * SYNC PORT sdtr .set 0fff0h sspcr .set 0fff1h * UART adtr .set 0fff4h aspcr .set 0fff5h iosr .set 0fff6h brd .set 0fff7h * TIMER tcr .set 0fff8h prd .set 0fff9h tim .
Shared Program Code Example C–3. Header File With Interrupt Vector Declarations (vector.h) * File: * File vector.h * defines Interrupt vector labels * .sect ”vectors” b start ; reset vector – Jump to label start on reset b inpt1 ; INT1 interrupt b inpt23 ; INT2/INT3 interrupt b timer ; TINT Timer interrupt b codrx ; RX_Sync interrupt b codtx ; TX_SYNC interrupt b uart ; TX/RX Uart port interrupt ; Reserved and s/w interrupt vector locations .space 45*16 ; Directive for filling zeros in PM space .
Task-Specific Program Code C.3 Task-Specific Program Code Example C–4. Implementing Simple Delay Loops (delay.asm) * File: * Function: delay.asm Delay loop. XF and I/O 3 pins toggle after each delay * * .title ”Delay routine” ; Title .copy ”init.h” ; Variable and register declaration .copy ”vector.h” ; Vector label declaration .
Task-Specific Program Code Example C–5. Testing and Using the Timer (timer.asm) * * * * * File: timer.asm * Function: Timer test code * PRD=0x00ff,TDDR=f @ 50ns, gives an interrupt interval=205us * PRD=0xffff,TDDR=0 @ 50ns, gives an interrupt interval=3.27ms* Timer interval measurable on I/O 2,3 or xf pins * start: wait: timer: inpt1: inpt23: codtx: codrx: uart: .title .copy .copy .
Task-Specific Program Code Example C–6. Testing and Using Interrupt INT1 (intr1.asm) * * * * File: intr1.asm * Function: Interrupt test code * For each INT1 interrupt XF,I/O pins IO3 and IO2 will toggle and * transmit char ’c’ through UART * start: wait: inpt1: timer: inpt23: uart: codtx: codrx: C-10 .title .copy .copy .text clrc ldp setc splk splk splk out splk out splk out splk out mar lar lar splk splk splk clrc clrc out idle clrc b ”Interrupt 1 Test” ”init.h” ”vector.
Task-Specific Program Code Example C–7. Implementing a HOLD Operation (hold.asm) * * * * File: hold.asm Function: HOLD test code Check for HOLDA toggle for HOLD requests in MODE 0 Check for XF toggle on HOLD/INT1 requests in MODE 1 icr icrshdw * * * * .title ” HOLD Test ” ; Title .mmregs .set 0FFECh ; Interrupt control register in I/O space .set 060h ; scratch pad location * Interrupt vectors .text reset B main int1h B int1_hold .
Task-Specific Program Code Example C–8. Testing and Using Interrupts INT2 and INT3 (intr23.asm) * * * * File: intr23.asm Function: Interrupt test code Interrupt on INT2 or INT3 will toggle IO3 and IO2 bits and icr value copied in the Buffer @300 start: wait: inpt23: skip: timer: inpt1: uart: codtx: codrx: C-12 .title ” Interrupt 2/3 Test” .copy ”init.h” .copy ”vector.h” .
Task-Specific Program Code Example C–9. Asynchronous Serial Port Transmission (uart.asm) * File: uart.asm * Function: UART Test Code * Continuously sends ’’C203 UART is fine’ at 1200 baud. start: .title .copy .copy .text clrc ldp setc * * * ” UART Test” ”init.h” ”vector.
Task-Specific Program Code Example C–9. Asynchronous Serial Port Transmission (uart.asm) (Continued) wait: uart: skip: inpt1: inpt23: timer: codtx: codrx: lar lar mar clrc clrc idle b setc splk out mar banz lar lar splk clrc ret ret ret ret ret ret .
Task-Specific Program Code Example C–10. Loopback to Verify Transmissions of Asynchronous Serial Port (echo.
Task-Specific Program Code Example C–11. Testing and Using Automatic Baud-Rate Detection on Asynchronous Serial Port (autobaud.asm) * File: * Function: * * * autobaud.asm UART,auto baud test Locks to incoming baud rate if the first character is ”A” or ”a” & continuously echoes data received through the port.
Task-Specific Program Code Example C–11. Testing and Using Automatic Baud-Rate Detection on Asynchronous Serial Port (autobaud.asm) (Continued) uart: rcv: skip: inpt1: inpt23: timer: codtx: codrx: setc in bit bcnd splk out splk out in bit bcnd in out mar banz lar lar splk clrc ret ret ret ret ret ret .
Task-Specific Program Code Example C–12. Testing and Using Asynchronous Serial Port Delta Interrupts (bitio.asm) * File: * Function: * * * * * * start: bitio.asm Delta interrupt test code Accepts delta interrupt on IO pins 3 and 2 If bit level changes on bit 7, send character ’c’ through UART & toggle xf pin. If bit level changes on bit 6, send character ’i’ through UART & toggle xf pin. The delta bits are cleared after interrupt service .title .copy .copy .
Task-Specific Program Code Example C–12. Testing and Using Asynchronous Serial Port Delta Interrupts(bitio.asm) (Continued) uart: poll: poll1: inpt1: inpt23: timer: codtx: codrx: setc in bit xf 68h,iosr 68h,8 bcnd clrc out splk out poll,ntc tc 65h, adtr #0080h,6bh 6bh,iosr clrc splk clrc ret in bit bcnd clrc out splk out clrc splk clrc ret ret ret ret ret ret .
Task-Specific Program Code Example C–13. Synchronous Serial Port Continuous Mode Transmission (ssp.asm) * File: * Function: * * start: loop: codtx: codrx: inpt1: inpt23: timer: uart: C-20 ssp.asm Continuous transmit in CONTINUOUS mode Internal shift clock and frame sync Transmit FIFO level is set to 4 * * * * .title .copy .copy .text clrc ldp setc splk out splk out splk out ”SSP Continuous mode” ”init.h” ”vector.
Task-Specific Program Code Example C–14. Using Synchronous Serial Port With Codec Device (ad55.asm) * File: * Function: * * start: main: ad55.asm Burst mode simple loop back on AD55 CODEC CODEC master clock 10 MHz Simple I/O at 9.6-kHz sampling .title .copy .copy .text clrc ldp setc splk out splk out splk out splk splk mar lar lar * 0 0 R/W’ *D15 14 13 splk splk splk splk splk splk splk out out out clrc loop: clrc idle b * * * * ”AD55 codec simple I/O” ; Title ”init.
Task-Specific Program Code Example C–14. Using Synchronous Serial Port With Codec Device (ad55.asm) (Continued) codtx: splk clrc ret #0010h, ifr intm ; clear tx intr flag codrx: setc in lacc and sacl out mar banz lar lar splk clrc ret ret ret ret ret .
Introduction to Generating Boot Loader Code C.4 Introduction to Generating Boot Loader Code The ’C2xx on-chip boot loader boots software from an 8-bit external EPROM to a 16-bit external RAM at reset. This section introduces to the procedure for using Texas Instruments development tools to generate the code that will be loaded into the EPROM. Note: The procedure in this section is given only as an example. This procedure may have to be modified to suit different applications.
Introduction to Generating Boot Loader Code Example C–15.
Appendix AppendixDA Submitting ROM Codes to TI The size of a printed circuit board is a consideration in many DSP applications. To make full use of the board space, Texas Instruments offers this ROM code option that reduces the chip count and provides a single-chip solution.
Submitting ROM Codes to TI Figure D–1.
Submitting ROM Codes to TI The TMS320 ROM code may be submitted in one of the following forms: - 5-1/4-in floppy: COFF format from macro-assembler/linker (preferred) Modem (BBS): COFF format from macro-assembler/linker EPROM (others): TMS27C64 PROM: TBP28S166, TBP28S86 When code is submitted to TI for masking, the code is reformatted to accommodate the TI mask-generation system.
Appendix AppendixEA Design Considerations for Using XDS510 Emulator This appendix assists you in meeting the design requirements of the Texas Instruments XDS510 emulator with respect to IEEE-1149.1 designs and discusses the XDS510 cable (manufacturing part number 2617698-0001). This cable is identified by a label on the cable pod marked JTAG 3/5V and supports both standard 3-V and 5-V target system power inputs.
Designing Your Target System’s Emulator Connector (14-Pin Header) E.1 Designing Your Target System’s Emulator Connector (14-Pin Header) JTAG target devices support emulation through a dedicated emulation port. This port is accessed directly by the emulator and provides emulation functions that are a superset of those specified by IEEE 1149.1. To communicate with the emulator, your target system must have a 14-pin header (two rows of seven pins) with the connections that are shown in Figure E–1.
Designing Your Target System’s Emulator Connector (14-Pin Header) Table E–1. 14-Pin Header Signal Descriptions Emulator† State Target† State Emulation pin 0 I I/O EMU1 Emulation pin 1 I I/O GND Ground PD(VCC) Presence detect. Indicates that the emulation cable is connected and that the target is powered up. PD should be tied to VCC in the target system. I O TCK Test clock. TCK is a 10.368-MHz clock source from the emulation cable pod. This signal can be used to drive the system test clock.
Bus Protocol E.2 Bus Protocol The IEEE 1149.1 specification covers the requirements for the test access port (TAP) bus slave devices and provides certain rules, summarized as follows: - The TMS and TDI inputs are sampled on the rising edge of the TCK signal of the device. The TDO output is clocked from the falling edge of the TCK signal of the device. When these devices are daisy-chained together, the TDO of one device has approximately a half TCK cycle setup time before the next device’s TDI signal.
Emulator Cable Pod E.3 Emulator Cable Pod Figure E–2 shows a portion of the emulator cable pod. The functional features of the pod are: - TDO and TCK_RET can be parallel-terminated inside the pod if required by the application. By default, these signals are not terminated. TCK is driven with a 74LVT240 device. Because of the high-current drive (32-mA IOL/IOH), this signal can be parallel-terminated. If TCK is tied to TCK_RET, you can use the parallel terminator in the pod.
Emulator Cable Pod Signal Timing E.4 Emulator Cable Pod Signal Timing Figure E–3 shows the signal timings for the emulator cable pod. Table E–2 defines the timing parameters illustrated in the figure. These timing parameters are calculated from values specified in the standard data sheets for the emulator and cable pod and are for reference only. Texas Instruments does not test or guarantee these timings. The emulator pod uses TCK_RET as its clock source for internal synchronization.
Emulation Timing Calculations E.5 Emulation Timing Calculations Example E–1 and Example E–2 help you calculate emulation timings in your system. For actual target timing parameters, see the appropriate data sheet for the device you are emulating.
Emulation Timing Calculations Example E–1. Key Timing for a Single-Processor System Without Buffers t pd ƪ ǒTCK_RET-TMS TDI t pd ƫ t ǒ Ǔ)t ǒ Ǔ + ń Ǔ t ) 10 ns) + (20 ns0.4 + 75 ns, or 13.3 MHz t ǒ Ǔ)t ǒ Ǔ + Ǔ t + (15 ns0.4) 3 ns) + 45 ns, or 22.2 MHz d TMSmax su TTMS TCKfactor ǒTCK_RET–TDO ƪ d TTDO su TDOmin ƫ TCKfactor In this case, because the TCK_RET-to-TMS/TDI path requires more time to complete, it is the limiting factor. Example E–2.
Emulation Timing Calculations In a multiprocessor application, it is necessary to ensure that the EMU0 and EMU1 lines can go from a logic low level to a logic high level in less than 10 µs, this parameter is called rise time, tr. This can be calculated as follows: tr = 5(Rpullup × Ndevices × Cload_per_device) = 5(4.7 kW × 16 × 15 pF) = 5(4.7 × 103 W × 16 × 15 = no –12 F) = 5(1128 × 10 –9 ) = 5.
Connections Between the Emulator and the Target System E.6 Connections Between the Emulator and the Target System It is extremely important to provide high-quality signals between the emulator and the JTAG target system. You must supply the correct signal buffering, test clock inputs, and multiple processor interconnections to ensure proper emulator and target system operation. Signals applied to the EMU0 and EMU1 pins on the JTAG target device can be either input or output.
Connections Between the Emulator and the Target System Figure E–5. Emulator Connections With Signal Buffering Greater than 6 inches VCC VCC JTAG device Emulator header EMU0 EMU1 TRST TMS TDI TDO TCK 13 14 2 1 3 7 11 9 EMU0 PD 5 EMU1 TRST GND TMS GND TDI GND TDO GND TCK GND 4 6 8 10 12 TCK_RET GND The EMU0 and EMU1 signals must have pullup resistors connected to VCC to provide a signal rise time of less than 10 µs. A 4.7-kΩ resistor is suggested for most applications.
Connections Between the Emulator and the Target System E.6.2 Using a Target-System Clock Figure E–6 shows an application with the system test clock generated in the target system. In this application, the emulator’s TCK signal is left unconnected. Figure E–6.
Connections Between the Emulator and the Target System E.6.3 Configuring Multiple Processors Figure E–7 shows a typical daisy-chained multiprocessor configuration that meets the minimum requirements of the IEEE 1149.1 specification. The emulation signals are buffered to isolate the processors from the emulator and provide adequate signal drive for the target system. One of the benefits of this interface is that you can slow down the test clock to eliminate timing problems.
Physical Dimensions for the 14-Pin Emulator Connector E.7 Physical Dimensions for the 14-Pin Emulator Connector The JTAG emulator target cable consists of a 3-foot section of jacketed cable that connects to the emulator, an active cable pod, and a short section of jacketed cable that connects to the target system. The overall cable length is approximately 3 feet 10 inches. Figure E–8 and Figure E–9 (page E-15) show the physical dimensions for the target cable pod and short cable.
Physical Dimensions for the 14-Pin Emulator Connector Figure E–9. 14-Pin Connector Dimensions 0.20 i nch, nominal Cable 0.66 inch, nominal Connector, side view 0.100 inch, nominal (pin spacing) Key, pin 6 13 14 11 12 9 10 7 8 5 6 3 4 1 2 Cable 0.87 inch, nominal 0.
Emulation Design Considerations E.8 Emulation Design Considerations This section describes the use and application of the scan path linker (SPL), which can simultaneously add all four secondary JTAG scan paths to the main scan path. It also describes the use of the emulation pins and the configuration of multiple processors. E.8.1 Using Scan Path Linkers You can use the TI ACT8997 scan path linker (SPL) to divide the JTAG emulation scan path into smaller, logically connected groups of 4 to 16 devices.
Emulation Design Considerations Figure E–10. Connecting a Secondary JTAG Scan Path to a Scan Path Linker SPL DTCK TDI TDI DTDO0 TMS TMS DTMS0 TCK TCK DTDI0 TDO DTDO1 DTMS1 TRST TDO ... TRST JTAG 0 DTDI1 TDI DTDO2 TMS DTMS2 TCK DTDI2 TRST DTDO3 TDO JTAG N DTMS3 DTDI3 The TRST signal from the main scan path drives all devices, even those on the secondary scan paths of the SPL.
Emulation Design Considerations E.8.2 Emulation Timing Calculations for a Scan Path Linker (SPL) Example E–3 and Example E–4 help you to calculate the key emulation timings in the SPL secondary scan path of your system. For actual target timing parameters, see the appropriate device data sheet for your target device.
Emulation Design Considerations Of the following two cases, the worst-case path delay is calculated to determine the maximum system test clock frequency. ƪ+ Example E–3. Key Timing for a Single-Processor System Without Buffering (SPL) t pd ǒTCK-DTMSǓ td t TCKfactor + (31 ns ) 20.4ns ) 10 ns) + 107.5 ns, or 9.3 MHz t ǒ Ǔ)t ǒ Ǔ)t ǒ Ǔ+ t + (15 ns ) 160.4ns ) 7 ns) + 9.5 ns, or 10.
Emulation Design Considerations E.8.3 Using Emulation Pins The EMU0/1 pins of TI devices are bidirectional, 3-state output pins. When in an inactive state, these pins are at high impedance. When the pins are active, they provide one of two types of output: - - Signal Event. The EMU0/1 pins can be configured via software to signal internal events. In this mode, driving one of these pins low can cause devices to signal such events.
Emulation Design Considerations Figure E–11. EMU0/1 Configuration to Meet Timing Requirements of Less Than 25 ns Target board 1 Backplane Pullup resistor Device 1 XCNT_ENABLE EMU0/1 ... Opencollector drivers ... Device n EMU0/1-IN TCK Pullup resistor Target board m To emulator EMU0 Opencollector drivers Pullup resistor Device 1 Notes: EMU0/1 ... EMU0/1-OUT ... ... PAL ... Device n 1) The low time on EMU0/1-IN should be at least one TCK cycle and less than 10 ms.
Emulation Design Considerations - - - R The bused EMU0/1 signals go into a programmable logic array device PAL whose function is to generate a low pulse on the EMU0/1-IN signal when a low level is detected on the EMU0/1-OUT signal. This pulse must be longer than one TCK period to affect the devices but less than 10 µs to avoid possible conflicts or retriggering once the emulation software clears the device’s pins.
Emulation Design Considerations Figure E–13. EMU0/1 Configuration With Additional AND Gate to Meet Timing Requirements of Greater Than 25 ns Target board 1 Backplane Pullup resistor Device 1 XCNT_ENABLE EMU0/1 ... Opencollector drivers ... Device n EMU0/1-IN Pullup resistor Target board m Opencollector drivers Circuitry required for >25-ns rise/fall time modification AND To emulator EMU1 EMU1 Up to m boards Pullup resistor EMU0/1 ... To Emulator EMU0 TCK Notes: ... EMU0/1-OUT ... .
Emulation Design Considerations You do not need to have devices on one target board stop devices on another target board using the EMU0/1 signals (see the circuit in Figure E–14). In this configuration, the global-stop capability is lost. It is important not to overload EMU0/1 with more than 16 devices. Figure E–14. EMU0/1 Configuration Without Global Stop Target board 1 Pullup resistor ... Pullup resistor Device 1 To emulator ... EMU0/1 Device n EMU0/1 ... ... Target board m Pullup resistor ...
Emulation Design Considerations Figure E–15. TBC Emulation Connections for n JTAG Scan Paths Clock TBC VCC TCKI JTAG0 TDO TDI TMS0 TMS TMS1 EMU0 TMS2/EVNT0 EMU1 TMS3/EVNT1 TRST TMS4/EVNT2 TCK TMS5/EVNT3 TDO TCKO TDI0 TDI1 TDI JTAGN TMS EMU0 EMU1 TRST TCK TDO In the system design shown in Figure E–15, the TBC emulation signals TCKI, TDO, TMS0, TMS2/EVNT0, TMS3/EVNT1, TMS5/EVNT3, TCKO, and TDI0 are used, and TMS1, TMS4/EVNT2, and TDI1 are not connected.
Appendix AppendixFA Glossary A A0–A15: Collectively, the external address bus; the 16 pins are used in parallel to address external data memory, program memory, or I/O space. ACC: See accumulator. ACCH: Accumulator high word. The upper 16 bits of the accumulator. See also accumulator. ACCL: Accumulator low word. The lower 16 bits of the accumulator. See also accumulator.
Glossary analog-to-digital (A/D) converter: A circuit that translates an analog signal to a digital signal. AR: See auxiliary register. AR0–AR7: Auxiliary registers 0 through 7. See auxiliary register. ARAU: See auxiliary register arithmetic unit (ARAU). ARB: See auxiliary register pointer buffer (ARB). ARP: See auxiliary register pointer (ARP). ARSR: Asynchronous serial port receive shift register.
Glossary B B0: An on-chip block of dual-access RAM that can be configured as either data memory or program memory, depending on the value of the CNF bit in status register ST1. B1: An on-chip block of dual-access RAM available for data memory. B2: An on-chip block of dual-access RAM available for data memory. baud-rate divisor register (BRD): A register for the asynchronous serial port that is used to set the serial port’s baud rate. BI bit: Break interrupt bit.
Glossary CALU: See central arithmetic logic unit (CALU). carry bit: Bit 9 of status register ST1; used by the CALU for extended arithmetic operations and accumulator shifts and rotates. The carry bit can be tested by conditional instructions. central arithmetic logic unit (CALU): The 32-bit wide main arithmetic logic unit for the ’C2xx CPU that performs arithmetic and logic operations. It accepts 32-bit values for operations, and its 32-bit output is held in the accumulator.
Glossary clock mode (clock generator): One of the modes which sets the internal CPU clock frequency to a fraction or multiple of the frequency of the input clock signal CLKIN. The ’C209 has two clock modes (÷2 and ×2); other ’C2xx devices have four clock modes (÷2, ×1, ×2, and ×4). clock mode (synchronous serial port): See clock mode bit (MCM).
Glossary current data page: The data page indicated by the content of the data page pointer (DP). See also data page; DP. D D0–D15: Collectively, the external data bus; the 16 pins are used in parallel to transfer data between the ’C2xx and external data memory, program memory, or I/O space. DARAM: Dual-access RAM. RAM that can be accessed twice in a single CPU clock cycle. For example, your code can read from and write to DARAM in the same clock cycle. DARAM configuration bit (CNF): See CNF bit.
Glossary decode phase: The phase of the pipeline in which the instruction is decoded. See also pipeline; instruction-fetch phase; operand-fetch phase; instruction-execute phase. delta interrupt: An asynchronous serial port interrupt (TXRXINT) that is generated if a change takes place on one of these general-purpose I/O pins: IO0, IO1, IO2, or IO3. digital loopback mode: A synchronous serial port test mode in which the receive pins are connected internally to the transmit pins on the same device.
Glossary DRAB: See data-read address bus (DRAB). DRDB: See data read bus (DRDB). DS: Data memory select pin. The ’C2xx asserts DS to indicate an access to external data memory (local or global). DSWS: Data-space wait-state bit(s). A value in the wait-state generator control register (WSGR) that determines the number of wait states applied to reads from and writes to off-chip data space. On the ’C209, DSWS is bit 1 of the WSGR; on other ’C2xx devices, DSWS is bits 8–6. dual-access RAM: See DARAM.
Glossary FR0/FR1: FIFO receive-interrupt bits. Bits 8 and 9 of the synchronous serial port control register (SSPCR); together they set an interrupt trigger condition based on the number of words in the receive FIFO buffer. frame synchronization (frame sync) mode: One of two modes in the synchronous serial port that determine whether frame synchronization pulses are necessary between consecutive data transfers. See also burst mode; continuous mode.
Glossary G general-purpose input/output pins: Pins that can be used to accept input signals and/or send output signals but are not linked to specific uses. These pins are the input pin BIO, the output pin XF, and the input/output pins IO0, IO1, IO2, and IO3. (IO0–IO3 are not available on the ’C209.) global data space: One of the four ’C2xx address spaces. The global data space can be used to share data with other processors within a system and can serve as additional data space. See also local data space.
Glossary IC: (Used in earlier documentation.) See interrupt control register (ICR). ICR: See interrupt control register (ICR). IFR: See interrupt flag register (IFR). immediate addressing: One of the methods for obtaining data values used by an instruction; the data value is a constant embedded directly into the instruction word; data memory is not accessed. immediate operand/immediate value: A constant given as an operand in an instruction that is using immediate addressing.
Glossary INT1–INT3: Three external pins used to generate general-purpose hardware interrupts. internal interrupt: A hardware interrupt caused by an on-chip peripheral. interrupt: A signal sent to the CPU that (when not masked or disabled) forces the CPU into a subroutine called an interrupt service routine (ISR). This signal can be triggered by an external device, an on-chip peripheral, or an instruction (INTR, NMI, or TRAP).
Glossary IO0–IO3 bits: Bits 0–3 of the IOSR. When pins IO0–IO3 are configured as inputs, these bits reflect the current logic levels on the pins. For example, the IO0 bit reflects the level on the IO0 pin. See also CIO0–CIO3 bits; DIO0–DIO3 bits. IO0–IO3 pins: Four pins that can be individually configured as inputs or outputs. These pins can be used for interfacing the asynchronous serial port or as general-purpose I/O pins. See also CIO0–CIO3 bits; DIO0–DIO3 bits; IO0–IO3 bits.
Glossary LSB: Least significant bit. The lowest order bit in a word. When used in plural form (LSBs), refers to a specified number of low-order bits, beginning with the lowest order bit and counting to the left. For example, the four LSBs of a 16-bit value are bits 0 through 3. See also MSB. M machine cycle: See CPU cycle. maskable interrupt: A hardware interrupt that can be enabled or disabled through software. See also nonmaskable interrupt. master clock output signal: See CLKOUT1.
Glossary MSTACK: See micro stack. multiplier: A part of the CPU that performs 16-bit × 16-bit multiplication and generates a 32-bit product. The multiplier operates using either signed or unsigned 2s-complement arithmetic. N next AR: See next auxiliary register. next auxiliary register: The register that will be pointed to by the auxiliary register pointer (ARP) when an instruction that modifies ARP is finished executing. See also auxiliary register; current auxiliary register.
Glossary OV bit: Overflow flag bit. Bit 12 of status register ST0; indicates whether the result of an arithmetic operation has exceeded the capacity of the accumulator. overflow (in a register): A condition in which the result of an arithmetic operation exceeds the capacity of the register used to hold that result. overflow (in the synchronous serial port): A condition in which the receive FIFO buffer of the port is full and another word is received in the RSR.
Glossary pipeline: A method of executing instructions in an assembly line fashion. The ’C2xx pipeline has four independent phases. During a given CPU cycle, four different instructions can be active, each at a different stage of completion. See also instruction-fetch phase; instruction-decode phase; operand-fetch phase; instruction-execute phase. PLL: Phase lock loop circuit. PM bits: See product shift mode bits (PM).
Glossary program control logic: Logic circuitry that decodes instructions, manages the pipeline, stores status of operations, and decodes conditional operations. program counter (PC): A register that indicates the location of the next instruction to be executed. program read bus (PRDB): A 16-bit internal bus that carries instruction code and immediate operands, as well as table information, from program memory to the CPU. PS: Program select pin.
Glossary receive interrupt (asynchronous serial port): An interrupt (TXRXINT) caused during reception by any one of these events: the ADTR holds a new character; overrun occurs; a framing error occurs; a break has been detected on the RX pin; a character A or a has been detected in the ADTR by the automatic baud-rate detection logic. receive interrupt (synchronous serial port): See RINT.
Glossary RPTC: See repeat counter (RPTC). RRST: Receive reset bit. Bit 4 of the synchronous serial port control register (SSPCR); resets the receiver portion of the synchronous serial port. RS: Reset pin. When driven low, causes a reset on any ’C2xx device, including the ’C209. RS: Reset pin. (On the ’C209 only) When driven high, causes a reset. RSR: Receive shift register. Shifts data serially into the synchronous serial port from the DR pin. See also XSR. R/W: Read/write pin.
Glossary single-access RAM: See SARAM. slave phase: See latch phase. SOFT bit (asynchronous serial port): Bit 14 in the asynchronous serial port control register (ASPCR); a special emulation bit that is used in conjunction with bit 15 (FREE) to determine the state of an asynchronous serial port transfer when a software breakpoint is encountered during emulation. When FREE = 0, SOFT determines the emulation mode. See also FREE bit (asynchronous serial port).
Glossary status registers ST0 and ST1: Two 16-bit registers that contain bits for determining processor modes, addressing pointer values, and indicating various processor conditions and arithmetic logic results. These registers can be stored into and loaded from data memory, allowing the status of the machine to be saved and restored for subroutines. STB bit: Stop bit selector.
Glossary TIM bit: Transmit interrupt mask bit. Bit 8 of the asynchronous serial port control register (ASPCR); enables or disables transmit interrupts of the asynchronous serial port. TIM register: See timer counter register (TIM). timer counter register (TIM): A 16-bit memory-mapped register that holds the main count for the on-chip timer. See also timer prescaler counter (PSC).
Glossary transmit mode (TXM) bit: Bit 3 of the synchronous serial port control register (SSPCR); determines whether the source signal for frame synchronization is external or internal. transmit pin (asynchronous serial port): See TX pin. transmit pin (synchronous serial port): See DX pin. transmit/receive interrupt (TXRXINT): The CPU interrupt used to respond to a delta interrupt, receive interrupt, or transmit interrupt from the asynchronous serial port.
Glossary URST: Reset asynchronous serial port bit. Bit 13 of the asynchronous serial port control register (ASPCR); resets the asynchronous port. V vector: See interrupt vector. vector location: See interrupt vector location. W wait state: A CLKOUT1 cycle during which the CPU waits when reading from or writing to slower external memory. wait-state generator: An on-chip peripheral that generates a limited number of wait states for a given off-chip memory space (program, data, or I/O).
Glossary Z zero fill: Fill the unused low or high order bits in a register with zeros.
Index Index * operand 6-10 *+ operand 6-10 *– operand 6-10 *0+ operand 6-10 *0– operand 6-10 *BR0+ operand 6-11 *BR0– operand 6-11 14-pin connector, dimensions E-15 14-pin header header signals E-2 JTAG E-2 4-level pipeline operation 5-7 A A0–A15 (external address bus) definition 4-3 shown in figure 4-6, 4-10, 4-13, 4-15, 4-26 ABS instruction 7-21 absolute value (ABS instruction) 7-21 accumulator definition F-1 description 3-9 shifting and storing high and low words, diagrams 3-11 accumulator instructions
Index accumulator instructions (continued) store high byte of accumulator to data memory (SACH) 7-148 store low byte of accumulator to data memory (SACL) 7-150 subtract conditionally from accumulator (SUBC) 7-180 subtract PREG from accumulator (SPAC) 7-160 subtract PREG from accumulator and load TREG (LTS) 7-100 subtract PREG from accumulator and multiply (MPYS) 7-118 subtract PREG from accumulator and square specified value (SQRS) 7-170 subtract value and logical inversion of carry bit from accumulator (S
Index asynchronous serial port (continued) baud-rate detection logic detecting A or a character (ADC bit) 10-10 enabling/disabling (CAD bit) 10-8 block diagram 10-3 components 10-3 configuration 10-7 delta interrupts 10-17 enabling/disabling (DIM bit) 10-8 emulation modes (FREE and SOFT bits) 10-7 features 10-1 interrupts (TXRXINTs) flag bit (TXRXINT) 5-21 introduction 10-5 mask bit in IMR (TXRXINT) 5-23 mask bits in ASPCR (DIM, TIM, RIM) 10-8 priority 5-16 three types 10-17 vector location 5-16 introducti
Index boot loader 4-14 to 4-22 boot source (EPROM) choosing an EPROM 4-14 connecting the EPROM 4-15 programming the EPROM 4-16 diagram 4-14 to 4-22 enabling 4-17 execution 4-18 generating code for EPROM C-23 to C-24 program code 4-21 B B instruction 7-39 BACC instruction 7-40 BANZ instruction 7-41 baud-rate detection procedure 10-14 divisor register (BRD) 10-13 generator 10-4 BCND instruction BI bit BR (bus request pin) definition 4-3 shown in figure 4-13, 4-15 7-43 10-10 BIO pin 8-17 to 8-18
Index bus request pin (BR) definition 4-3 shown in figure 4-13, 4-15 buses block diagram 2-4 data read bus (DRDB) 2-3 data write bus (DWEB) 2-3 data-read address bus (DRAB) 2-3 data-write address bus (DWAB) 2-3 program address bus (PAB) definition 2-3 used in program-memory address generation 5-3 program read bus (PRDB) 2-3 C C (carry bit) affected during SFL and SFR instructions 7-157 to 7-159 definition 3-16 involved in accumulator events 3-10 used during ROL and ROR instructions 7-144 to 7-146 ’C209 de
Index CMPR instruction 7-65 CNF (DARAM configuration bit) code compatibility codec, definition 3-16 1-6 F-5 conditional instructions 5-10 to 5-13 conditional branch 5-11 to 5-13 conditional call 5-12 to 5-13 conditional return 5-12 to 5-13 conditions that may be tested 5-10 stabilization of conditions 5-11 using multiple conditions 5-10 configuration memory global data 4-11 RAM (dual-access) D ’C203 4-33 ’C204 4-36 ’C209 11-8 RAM (single-access) 11-7 ROM ’C204 4-36 ’C209 11-7 multiprocessor E-13
Index data memory select pin (DS) definition 4-3 shown in figure 4-10, 4-13 data page 0 4-8 caution about test/emulation addresses data page pointer (DP) caution about initializing DP 6-5 definition 3-16 load (LDP instruction) 7-83 role in direct addressing 6-4 data read bus (DRDB) 2-3 data write bus (DWEB) 2-3 data-read address bus (DRAB) 2-3 data-scaling shifter at input of CALU 3-3 at output of CALU 3-11 data-write address bus (DWAB) delta interrupts description 10-17 enabling/disabling (DIM bit)
Index emulator cable pod E-5 connection to target system, JTAG mechanical dimensions E-14 to E-25 designing the JTAG cable E-1 emulation pins E-20 pod interface E-5 pod timings E-6 signal buffering E-10 to E-13 target cable, header design E-2 to E-3 enhanced instructions B-5 error conditions asynchronous serial port framing error (FE bit) 10-11 overrun (OE bit) 10-11 synchronous serial port burst mode 9-29 continuous mode 9-29 examples of ’C2xx program code 4-level pipeline operation 14-pin header heade
Index H hardware interrupts definition 5-15 nonmaskable external 5-27 priorities 5-16 types 5-15 hardware reset 5-33 header 14-pin E-2 dimensions, 14-pin E-2 HOLD (HOLD operation request pin) definition 4-4 use in HOLD operation 4-27 HOLD acknowledge pin (HOLDA) definition 4-4 use in HOLD operation 4-27 HOLD operation description 4-27 during reset 4-29 example 4-28 terminating correctly 4-29 HOLD operation request pin (HOLD) definition 4-4 use in HOLD operation 4-27 HOLD/INT1 bit in interrupt flag register
Index IMR (interrupt mask register) 5-22 to 5-38 bits ’C203/C204 5-23 ’C209 11-13 in interrupt acknowledgement process 5-19 quick reference A-7 IN instruction 7-69 IN0 bit 9-10 indirect addressing description 6-9 effects on auxiliary register pointer (ARP) 6-14 to 6-16 effects on current auxiliary register 6-14 to 6-16 examples 6-15 modifying auxiliary register content 6-17 opcode format 6-12 to 6-14 operands 6-10 operation types 6-14 to 6-16 options 6-9 possible opcodes 6-14 to 6-16 input clock modes ’C20
Index INT1 interrupt ’C203/C204 flag bit (HOLD/INT1) 5-22 mask bit (HOLD/INT1) 5-24 priority 5-16 vector location 5-16 ’C209 flag bit 11-12 mask bit 11-13 priority 11-10 vector location 11-10 INT2 bit (’C209) in interrupt flag register (IFR) 11-12 in interrupt mask register (IMR) 11-13 INT2 interrupt ’C203/C204 flag bits FINT2 5-26 INT2/INT3 5-22 masking/unmasking in ICR 5-27 masking/unmasking in IMR 5-23 priority 5-16 vector location 5-16 ’C209 flag bit 11-12 mask bit 11-13 priority 11-10 vector location
Index interrupt (continued) phases of operation 5-15 priorities ’C203/C204 5-16 ’C209 11-10 in interrupt acknowledgement process 5-19 registers interrupt control register (ICR) 5-24 interrupt flag register (IFR) 5-20 to 5-22 ’C209 11-12 interrupt mask register (IMR) 5-22 to 5-24 ’C209 11-13 software interrupt definition 5-15 instructions 5-27 special cases clearing ICR flag bits 5-25 clearing IFR flag bit after INTR instruction 5-21 clearing IFR flag bits set by serial port interrupts 5-21 controlling IN
Index mask bits asynchronous serial port control register (ASPCR) 10-8 interrupt control register (ICR) 5-24 interrupt mask register (IMR) 5-22 L LACC instruction 7-72 LACL instruction 7-75 LACT instruction 7-78 LAR instruction 7-80 latch phase of CPU cycle F-13 latency, interrupt 5-30 to 5-36 after execution of RET 5-32 during execution of CLRC INTM minimum latency 5-30 LDP instruction 7-83 local data memory address map ’C203 4-32 ’C204 4-35 ’C209 11-6 configuration RAM (dual-access) 5-31 ’C203 4-33 ’C
Index memory (continued) introduction 4-2 local data memory description 4-7 to 4-10 pages of (diagram) 4-7 on-chip memory, advantages 4-2 organization 4-2 overview 2-7 pins for external interfacing 4-3 program memory 4-5 to 4-6 address generation logic 5-2 address sources 5-3 RAM (dual-access) configuration ’C203 4-33 ’C204 4-36 ’C209 11-8 description 2-7 RAM (single-access) configuration 11-7 description 2-8 reset conditions 5-33 ROM configuration ’C204 4-36 ’C209 11-7 introduction 2-8 memory instructio
Index next program address register (NPAR) definition F-15 shown in figure 5-2 NMI hardware interrupt description 5-27 priority ’C203/C204 5-17 ’C209 11-11 vector location ’C203/C204 5-17 ’C209 11-11 NMI instruction 7-124 introduction 5-28 vector location ’C203/C204 5-17 ’C209 11-11 nonmaskable interrupts 5-27 definition 5-15 flow chart of operation 5-29 hardware-initiated 5-27 software-initiated 5-27 NOP instruction NORM instruction 7-125 7-126 NPAR (next program address register) definition F-15 shown
Index OUT instruction 7-132 output modes external count E-20 signal event E-20 output shifter 3-11 OV (overflow flag bit) 3-16 overflow in accumulator detecting (OV bit) 3-16 enabling/disabling overflow mode (OVM bit) 3-17 overflow in synchronous serial port burst mode 9-29 continuous mode 9-30 detecting (OVF bit) 9-10 overflow mode bit (OVM) 3-17 effects on accumulator 3-10 OVF bit 9-10 P PAB (program address bus) definition 2-3 used in program-memory address generation 5-3 PAC instruction 7-134 packages
Index PREG instructions (continued) load high bits of PREG (LPH) 7-85 set PREG output shift mode (SPM) 7-167 store high word of PREG to data memory (SPH) 7-161 store low word of PREG to data memory (SPL) 7-163 store PREG to accumulator (PAC instruction) 7-134 store PREG to accumulator and load TREG (LTP) 7-98 subtract PREG from accumulator (SPAC) 7-160 subtract PREG from accumulator and load TREG (LTS) 7-100 subtract PREG from accumulator and multiply (MPYS) 7-118 subtract PREG from accumulator and square
Index program memory (continued) configuration RAM (dual-access) RD (read select pin) definition 4-4 shown in figure 4-6, 4-10, 4-13, 4-15 ’C203 4-33 ’C204 4-36 ’C209 11-8 read select pin (RD) definition 4-4 shown in figure 4-6, 4-10, 4-13, 4-15 RAM (single-access) 11-7 ROM ’C204 4-36 ’C209 11-7 description 4-5 external interfacing 4-5 caution about proper timing 4-5 program memory select pin (PS) definition 4-3 shown in figure 4-6 program read bus (PRDB) 2-3 program-address generation (diagram) 5-2 p
Index registers (continued) mapped to data page 0 4-8 mapped to I/O space ’C203/C204 4-24 ’C209 11-9 accessing 4-25 quick reference A-1 to A-14 status registers ST0 and ST1 timer control register (TCR) 3-15 ’C203/C204 8-10 ’C209 11-16 counter register (TIM) 8-12, F-23 divide-down register (TDDR) ’C203/C204 8-12 ’C209 11-16 period register (PRD) 8-12, F-23 prescaler counter (PSC) ’C203/C204 8-11 ’C209 11-15 wait-state generator control register (WSGR) ’C203/C204 8-15 ’C209 11-17 repeat (RPT) instructio
Index S SACH instruction 7-148 SACL instruction 7-150 SAR instruction 7-152 SARAM (single-access RAM) configuration 11-7 definition F-20 description 2-8 SBRK instruction 7-154 scaling shifters input shifter 3-3 introduction 2-5 output shifter 3-11 product shifter 3-6 product shift modes 3-7 scan path linkers E-16 secondary JTAG scan chain to an SPL suggested timings E-22 usage E-16 E-17 scan paths, TBC emulation connections for JTAG scan paths E-25 scanning logic overview 2-13 SDTR (synchrono
Index status registers ST0 and ST1 addresses and reset values A-2 bits 3-15 clear control bit (CLRC instruction) 7-62 introduction 3-15 load (LST instruction) 7-87 load data page pointer (LDP instruction) 7-83 modify auxiliary register pointer (MAR instruction) 7-111 quick reference A-5 set control bit (SETC instruction) 7-155 set product shift mode (SPM instruction) 7-167 store (SST instruction) 7-172 STB bit 10-8 STRB (external access active strobe) SUB instruction 4-3 7-174 SUBB instruction 7-178
Index synchronous serial port (continued) troubleshooting bits for testing the port 9-27 error conditions TDI signal E-18 TDO signal TEMT bit underflow in transmitter burst mode 9-29 continuous mode 9-29 T E-14 E-1 to E-25 target system emulator connector, designing target-system clock E-2 E-12 TBLR instruction 7-186 TBLW instruction 7-189 3-14 TCK signal E-2, E-3, E-4, E-6, E-7, E-13, E-17, E-18, E-25 9-9 TCR (timer control register) ’C209 11-15 quick reference A-9 8-10 to 8-12 TDDR (timer
Index timer control register (TCR) ’C209 11-15 quick reference A-9 8-10 to 8-12 timer counter register (TIM) 8-12, F-23 to F-26 timer period register (PRD) 8-12, F-23 to F-26 timing calculations E-7 to E-9, E-18 to E-26 TINT bit ’C203/C204 in interrupt flag register (IFR) 5-22 in interrupt mask register (IMR) 5-23 ’C209 in interrupt flag register (IFR) 11-12 in interrupt mask register (IMR) 11-13 TINT interrupt ’C203/C204 flag bit 5-22 mask bit 5-23 priority 5-16 vector location 5-16 ’C209 flag bit
Index TSS bit ’C203/C204 8-12 ’C209 11-16 TX pin 10-4 TXM bit 9-11 TXRXINT bit in interrupt flag register (IFR) 5-21 in interrupt mask register (IMR) 5-23 TXRXINT interrupt flag bit 5-21 mask bit in IMR 5-23 priority 5-16 vector location 5-16 U unconditional instructions unconditional branch 5-8 unconditional call 5-8 unconditional return 5-9 10-7 W wait states definition F-25 for data space ’C203/C204 8-15 ’C209 11-17 for I/O space ’C203/C204 8-15 ’C209 11-17 for program space ’C203/C204 8-15 ’C209
