Datasheet

Setup
4 C187EVK01 User’s Guide SNLU102-May 2012
Enabled
Low
VOD
Falling
Clock Edge
24-Bit
Operation
VDD
GND
Reserved for
Future Use
MODE0: HIGH
MODE1: LOW
Single Pixel In
Dual Pixel Out
(SIDO)
Figure 2: Default Jumper Settings
J3, J4 – LVDS OUTPUTS are brought out to two 2 x10 bank of header pins. Outputs for channel A are
brought out to J3 and outputs for channel B are brought out to J4. Note that each LVDS output is separated
from adjacent LVDS signals by one ground pin. By default, 100 ohm termination resistors are soldered onto
the EVM to allow for easy measuring and probing of the LVDS signals. If a cable is connected to J3 and/or
J4, these termination resistors (R57, R58, R62, R63, R64 and/or R65, R66, R67, R68, R69) must be
removed or the differential voltage swing will be reduced.
Figure 3: LVDS Output Connections (OA-J3 and OB-J4)
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