User’s Guide SNLU102--May 2012 C187EVK01 User’s Guide CONTENTS 1. INTRODUCTION........................................................................................................ 2 2. SETUP ....................................................................................................................... 3 3. BOARD LAYOUT ...................................................................................................... 6 4. SCHEMATIC .....................................................
Introduction 1. Introduction The Texas Instruments C187EVK01 evaluation module (EVM) helps designers evaluate the performance of the DS90C187 Low Power 1.8V Dual Pixel FPD-Link (LVDS) Serializer. The device operates off of a single 1.8V supply and supports input pixel clocks from 50 MHz to 185 MHz (Single In Dual Out) or 25 MHz to 105 MHz (Single/Dual In Single/Dual Out). The typical application, Single In Dual Out, is shown below. This EVM contains one Low Power 1.
Setup 2. Setup This section describes the jumpers and connectors on the EVK as well and how to properly connect, set up and use the C187EVK01. 2.1. Input/Output Connector Description JP1 – MODE1 is to be used in combination with JP2 (MODE0) to configure the DS90C187. Refer to Table 2. JP2 – MODE0 is to be used in combination with JP1 (MODE1) to configure the DS90C187. Refer to Table 2.
Setup VDD GND Reserved for Future Use Falling Clock Edge MODE0: HIGH MODE1: LOW 24-Bit Low Enabled Operation VOD Single Pixel In Dual Pixel Out (SIDO) Figure 2: Default Jumper Settings J3, J4 – LVDS OUTPUTS are brought out to two 2 x10 bank of header pins. Outputs for channel A are brought out to J3 and outputs for channel B are brought out to J4. Note that each LVDS output is separated from adjacent LVDS signals by one ground pin.
Setup J5, J6 – LVCMOS INPUTS for channel A are connected to the 2 x 30 bank of header pins, J5. LVCMOS inputs for channel B are connected to the 2 x 28 bank of header pins, J6. Note that each LVCMOS signal is paired with a ground signal. When attaching external test equipment or other hardware to this board it is important that there be sufficient ground connections to ensure good signal integrity for the input clock and data waveforms. 50 ohm terminations are provided for each LVCMOS input by default.
Setup 2.2. System Setup The input power jack (J1) should receive a voltage within the range of 1.71 V to 1.89 V referenced to ground which should be applied at J2, with JP4 set to LOW. Once, power has been applied to the board, JP4 (PDB pin) can be set to logic HIGH. After setting the PDB pin to HIGH, 1.8V clock and data can be transmitted to the EVM. If a cable is connected to J3 and/or J4, the termination resistors (R57, R58, R62, R63, R64 and/or R65, R66, R67, R68, R69) should be removed. 2.3.
Board Layout Figure 5: Top Assembly Layer H SNLU102-May 2012 Submit Documentation Feedback C187EVK01 User’s Guide 7
Board Layout Figure 6: Top Layer Routing 8 C187EVK01 User’s Guide SNLU102-May 2012 Submit Documentation Feedback
Board Layout Figure 7: Bottom Layer Routing SNLU102-May 2012 Submit Documentation Feedback C187EVK01 User’s Guide 9
2 GND 2 1 A52 93 OA_3OA_3+ OA_0+ OA_1- B30 OA_1+ A36 OA_2- B29 OA_2+ A35 OA_C- B28 OA_C+ A34 OA_3- B27 OA_3+ OA_1+ R62 100 0201 2 1 A37 OA_0+ R63 100 0201 OA_2+ OA_C+ 2 4 6 8 10 12 14 16 18 20 OA_0- VDD 1 2 3 VDD 1 2 3 VDD 1 2 3 VDD 1 2 3 VDD 1 2 3 VDD 1 2 3 VDD MODE1 GND MODE0 GND OA_1JP3 OA_2OA_C- RFB GND OA_3JP4 OA_3+ GND 2 1 OA_COA_C+ B31 1 2 3 JP2 J3 1 3 5 7 9 11 13 15 17 19 PDB GND JP5 R64 100 0201 1 OA_2+ A38 OA_0- 2 1 DAP GND A27 GND GND
Schematic GND GND 1 201 R322 49.9ohm 1 201 R312 49.9ohm 1 201 R302 49.9ohm 1 201 R292 49.9ohm 1 201 R282 49.9ohm 1 201 R272 49.9ohm 1 201 R262 49.9ohm 1 201 R252 49.9ohm 1 201 R242 49.9ohm 1 201 R232 49.9ohm 1 201 R222 49.9ohm 1 201 R212 49.9ohm 1 201 R202 49.9ohm 1 201 R192 49.9ohm 1 201 R182 49.9ohm 1 201 R172 49.9ohm 1 201 R162 49.9ohm 1 201 R152 49.9ohm 1 201 R142 49.9ohm 1 201 R132 49.9ohm 1 201 R122 49.9ohm 1 201 R112 49.9ohm 1 201 R102 49.9ohm 1 201 R92 49.9ohm 1 201 R82 49.
Schematic VDD_b + 2 R1 1 0 Ohm,0402 C16 2 2 GND VDD C21 C24 C27 + C19 22uF 2 2 2 GND VDDP 1 2 R5 1 0 Ohm,0402 C29 1 VDD_b 2 0.01uF 0.1uF 0.1uF 0.1uF C36 0.1uF 1 C35 0.1uF 2 1 1 C34 0.1uF 2 1 C33 0.1uF 2 1 C32 0.1uF 2 1 2 GND 2 1 C20 1 2 R2 1 0 Ohm,0402 1 VDD_b VDD_b 1 BANANA C31 0.1uF C18 22uF + 0.01uF 0.1uF 2 GND 1 C17 0.1uF 2 1 2 J2 2.
Schematic Table 3: C187EVK01 Bill of Materials Quantity 1 1 1 3 5 3 6 7 2 2 1 1 3 Reference C4 C5 C6 C16,C20,C29 C17,C21,C24,C27,C30 C18,C19,C28 C31,C32,C33,C34,C35,C36 JP1,JP2,JP3,JP4,JP5,JP6,JP7 J1,J2 J3,J4 J5 J6 R1,R2,R5 R6,R7,R8,R9,R10,R11,R12,R13,R14,R 15,R16,R17,R18,R19,R20,R21,R22,R2 3,R24,R25,R26,R27,R28,R29,R30,R31, R32,R33,R34,R35,R36,R37,R38,R39,R 40,R41,R42,R43,R44,R45,R46,R47,R4 8,R49,R50,R51,R52,R53,R54,R55,R56, 54 R59,R60,R61 R57,R58,R62,R63,R64,R65,R66,R67,R 10 68,R69 1 U1 SNLU102-May 20
FCC Warning This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general customer use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference.
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