Datasheet

BOARD LAYOUT GUIDELINES
BUF602
SBOS339B – OCTOBER 2005 – REVISED MAY 2008 ...................................................................................................................................................... www.ti.com
across the part. P
DL
will depend on the required b) Minimize the distance (< 0.25") from the
output signal and load but would, for a grounded power-supply pins to high-frequency 0.1µF
resistive load, be at a maximum when the output is decoupling capacitors. At the device pins, the ground
fixed at a voltage equal to 1/2 of either supply voltage and power-plane layout should not be in close
(for equal bipolar supplies). Under this condition, P
DL
proximity to the signal I/O pins. Avoid narrow power
= V
S
2
/(4 × R
L
). and ground traces to minimize inductance between
the pins and the decoupling capacitors. The
Note that it is the power in the output stage and not
power-supply connections should always be
into the load that determines internal power
decoupled with these capacitors. An optional supply
dissipation.
decoupling capacitor (0.1µF) across the two power
supplies (for bipolar operation) will improve
As a worst-case example, compute the maximum T
J
2nd-harmonic distortion performance. Larger (2.2µF
using a BUF602IDBV in the circuit on the front page
to 6.8µF) decoupling capacitors, effective at lower
operating at the maximum specified ambient
frequency, should also be used on the main supply
temperature of +85 ° C and driving a grounded 20 Ω
pins. These may be placed somewhat farther from
load.
the device and may be shared among several
P
D
= 10V × 5.8mA + 5
2
/(4 × 20 Ω ) = 370.5mW
devices in the same area of the PCB.
Maximum T
J
= +85 ° C + (0.37W × 150 ° C/W) = 141 ° C.
c) Careful selection and placement of external
components will preserve the high-frequency
Although this is still below the specified maximum
performance of the BUF602. Resistors should be a
junction temperature, system reliability considerations
very low reactance type. Surface-mount resistors
may require lower tested junction temperatures. The
work best and allow a tighter overall layout. Metal film
highest possible internal dissipation will occur if the
or carbon composition, axially-leaded resistors can
load requires current to be forced into the output for
also provide good high-frequency performance.
positive output voltages or sourced from the output
Again, keep their leads and PCB traces as short as
for negative output voltages. This puts a high current
possible. Never use wirewound type resistors in a
through a large internal voltage drop in the output
high-frequency application.
transistors. The output V-I plot (Figure 16 ) shown in
the Typical Characteristics include a boundary for 1W
d) Connections to other wideband devices on the
maximum internal power dissipation under these
board may be made with short, direct traces or
conditions.
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils) should be used,
Achieving optimum performance with a
preferably with ground and power planes opened up
high-frequency amplifier like the BUF602 requires
around them. If a long trace is required, and the 6dB
careful attention to board layout parasitics and
signal loss intrinsic to a doubly-terminated
external component types. Recommendations that
transmission line is acceptable, implement a matched
will optimize performance include:
impedance transmission line using microstrip or
a) Minimize parasitic capacitance to any AC ground
stripline techniques (consult an ECL design handbook
for all of the signal I/O pins. Parasitic capacitance on
for microstrip and stripline layout techniques). A 50 Ω
the output pins can cause instability: on the
environment is normally not necessary on board, and
noninverting input, it can react with the source
in fact, a higher impedance environment will improve
impedance to cause unintentional bandlimiting. To
distortion as shown in the distortion versus load plots.
reduce unwanted capacitance, a window around the
e) Socketing a high-speed part like the BUF602 is
signal I/O pins should be opened in all of the ground
not recommended. The additional lead length and
and power planes around those pins. Otherwise,
pin-to-pin capacitance introduced by the socket can
ground and power planes should be unbroken
create an extremely troublesome parasitic network
elsewhere on the board.
that makes it almost impossible to achieve a smooth,
stable frequency response. Best results are obtained
by soldering the BUF602 onto the board.
16 Submit Documentation Feedback Copyright © 2005 – 2008, Texas Instruments Incorporated
Product Folder Link(s): BUF602