Datasheet

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BUF12840

SBOS519A –OCTOBER 2010– REVISED JULY 2011

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READ/WRITE OPERATIONS The BUF12840 acknowledges each data byte. If the

master terminates communication early by sending a

The BUF12840 is able to read from a single DAC or

STOP or START condition on the bus, the specified

multiple DACs, or write to the register of a single

DAC, or multiple DACs in a single communication

not the same as updating the DAC output voltage;

transaction. DAC addresses for BANK0 begin with

see the Output Latch section.

00000, which corresponds to Register 0, through

01011, which corresponds to Register 11. DAC The process of updating multiple registers begins the

addresses for BANK1 begin with 10000, which same as when updating a single register. However,

corresponds to Register 0, through 11011, which instead of sending a STOP condition after writing the

corresponds to Register 11; see Table 5. Write addressed register, the master continues to send

commands are performed by setting the read/write bit data for the next register. The BUF12840

LOW. Setting the read/write bit HIGH performs a read automatically and sequentially steps through

transaction. subsequent registers as additional data are sent. The

process continues until all desired registers have

Writing

been updated or a STOP condition is sent.

To write to a single DAC register:

To write to multiple registers:

1. Send a START condition on the bus.

2. Send the device address and read/write bit =

LOW. The BUF12840 acknowledges this byte.

3. Send a DAC address byte. Bits D7−D5 are

3. Send either the Register 0 address byte to start

unused and should be set to 0. Bits D4−D0 are

at the first DAC or send the address of whichever

the DAC address; see Table 5. Only DAC

DAC is the first to be updated. The BUF12840

addresses 00000 to 01011 and 10000 to 11011

begins with this DAC and steps through

are valid and acknowledged.

subsequent DACs in sequential order.

4. Send two bytes of data for the specified DAC.

4. Send the bytes of data. The first two bytes are for

Begin by sending the most significant byte first

the DAC addressed in step 3. Its register is

(bits D15−D8, of which only bits D9 and D8 are

automatically updated after receiving the second

used), followed by the least significant byte (bits

byte. The next two are for the following DAC. The

D7−D0). The DAC register is updated after

DAC register is updated after receiving the fourth

receiving the second byte.

byte. The last two bytes are for Register 11. The

5. Send a STOP condition on the bus.

DAC register is updated after receiving the 24th

byte. For each DAC, begin by sending the most

See Figure 20.

significant byte (bits D15−D8, of which only bits

D9 and D8 have meaning), followed by the least

significant byte (bits D7−D0).

5. Send a STOP condition on the bus.

See Figure 21.

When the DAC registers are written through a

two-wire communication, changing the BKSEL pin

does not affect the communication because the

banks have different addresses. However, when

loading the DACs through an I

C communication, the

bank to be loaded is decided by the BKSEL pin.

Therefore, if the BKSEL pin is switched during a

two-wire load, the new value of BKSEL determines

the bank that is loaded.