Datasheet

Black White
Histogram
SourceDriver
SourceDriver
GammaReferences
BUF12840
AthroughL
Digital
Picture
Data
TimingController/Microcontroller
Gamma
Adjustment
Algorithm
BUF12840
www.ti.com SBOS519A –OCTOBER 2010– REVISED JULY 2011
DYNAMIC GAMMA CONTROL by using an additional control line connected to the
LD pin, or through software—writing a '1' in bit 15 of
Dynamic gamma control is a technique used to
any DAC register. For details on the operation of the
improve the picture quality in LCD TV applications.
double register input structure, see the Output Latch
The brightness in each picture frame is analyzed and
section.
the gamma curves are adjusted on a frame-by-frame
basis. The gamma curves are typically updated Example: Update all 12 registers simultaneously via
during the short vertical blanking period in the video software.
signal. Figure 19 shows a block diagram using the
Step 1: Check if the LD pin is placed in a high
BUF12840 for dynamic gamma control.
state.
Step 2: Write DAC registers 1-12 with bit 15
The BUF12840 is ideally suited for rapidly changing
always '0'.
the gamma curves as a result of its unique topology:
Step 3: Write any DAC register a second time
• Double register input structure to the DAC
with identical data. Make sure that bit 15 is '1'. All
• Fast serial interface
DAC channels are updated simultaneously after
• Simultaneous updating of all DACs by software.
receiving the last bit of data.
See the Read/Write Operations section to write to
all registers and the Output Latch sections. Example: Update all 12 registers simultaneously via
hardware.
END-USER SELECTED GAMMA CONTROL
Step 1: Toggle the BKSEL pin to the desired
gamma curve, either Bank0 or Bank1.
The double register input structure saves
Step 2: Toggle the LD pin low. When this occurs,
programming time by allowing updated DAC values to
all 12 internal DAC registers are updated after
be pre-stored into the first register bank. Storage of
1µs. The output then slews to the new voltage
this data can occur while a picture is still being
level. The time to change between two gamma
displayed. Because the data are only stored into the
voltage settings is then dependent on the slew
first register bank, the DAC output values remain
rate of the DAC plus the gamma buffer and the
unchanged—the display is unaffected. During the
change in voltage required. This value can be
vertical sync period, the DAC outputs (and therefore,
obtained by referring to the Large-Signal Step
the gamma voltages) can be quickly updated either
Response curve (Figure 9).
Figure 19. Dynamic Gamma Control
Copyright © 2010–2011, Texas Instruments Incorporated 17