Datasheet

SCL
SDA
t
(LOW)
t
R
t
F
t
(HDSTA)
t
(HDSTA)
t
(HDDAT)
t
(BUF)
t
(SUDAT)
t
(HIGH)
t
(SUSTA)
t
(SUSTO)
P S S P
BUF12840
www.ti.com SBOS519A –OCTOBER 2010– REVISED JULY 2011
TIMING DIAGRAMS Data Transfer: The number of data bytes transferred
between a START and a STOP condition is not
Figure 16 describes the timing operations on the
limited and is determined by the master device. The
BUF12840. Parameters for Figure 16 are defined in
receiver acknowledges data transfer.
Table 6. Bus definitions are:
Acknowledge: Each receiving device, when
Bus Idle: Both SDA and SCL lines remain high.
addressed, is obliged to generate an Acknowledge
bit. A device that acknowledges must pull down the
Start Data Transfer: A change in the state of the
SDA line during the Acknowledge clock pulse in such
SDA line, from high to low, while the SCL line is high,
a way that the SDA line is stable low during the high
defines a START condition. Each data transfer is
period of the Acknowledge clock pulse. Setup and
initiated with a START condition, denoted as S in
hold times must be taken into account. On a master
Figure 16.
receive, data transfer termination can be signaled by
Stop Data Transfer: A change in the state of the
the master generating a Not-Acknowledge on the last
SDA line from low to high while the SCL line is high
byte that has been transmitted by the slave.
defines a STOP condition. Each data transfer
terminates with a repeated START or STOP
condition, denoted as P in Figure 16.
Figure 16. Two-Wire Timing Diagram
Table 6. Timing Characteristics for Figure 16
STANDARD MODE FAST MODE HIGH-SPEED MODE
PARAMETER MIN MAX MIN MAX MIN MAX UNITS
SCL operating frequency f
(SCL)
0 0.1 0 0.4 0 3.4 MHz
Bus free time between ns
t
(BUF)
4000 600 160
STOP and START condition
Hold time after repeated
START condition. After this
t
(HDSTA)
100 100 100 ns
period, the first clock is
generated.
Repeated START condition
t
(SUSTA)
100 100 100 ns
setup time
STOP condition setup time t
(SUSTO)
100 100 100 ns
Data hold time t
(HDDAT)
1
(1)
0
(1)
0
(2)
ns
Data setup time t
(SUDAT)
250 100 10 ns
SCL clock low period t
(low)
4700 1300 160 ns
SCL clock high period t
(high)
4000 600 60 ns
Clock/data fall time t
F
300 300 160 ns
Clock/data rise time 300 300 160 ns
t
R
for SCLK ≤ 100kHz 1000 1000 ns
(1) For cases with a fall time of SCL less than 20ns and/or the rise time or fall time of SDA less than 20ns, the hold time should be greater
than 20ns.
(2) For cases with a fall time of SCL less than 10ns and/or the rise or fall time of SDA less than 10ns, the hold time should be greater than
10ns.
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