Datasheet

BKSEL

DACOut

10 sm

BANK0 BANK1BANK1 BANK0

10 sm

Case1 Case2 Case3 Case4

BANK1

Case5

BUF12840

SBOS519A –OCTOBER 2010– REVISED JULY 2011

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WRITE BOTH BANKS OF DAC REGISTERS Case 1: DAC_OUT updates to BANK1 because the

LD pin is low and BKSEL is high. Case 2: DAC_OUT

In slave mode, writes to both banks are accomplished

updates to BANK0 because BKSEL and the LD pin

through the two-wire bus; there are different register

are low. Case 3: DAC_OUT does not update when

address for the two banks. The BKSEL pin does not

the LD pin is high. Case 4: DAC_OUT updates to

impact writing to each of the banks. Table 5 details

BANK0 because the LD pin and BKSEL are low.

the DAC addresses for each bank.

Case 5: DAC_OUT updates to BANK1 because the

LD pin is low and BKSEL is high.

DAC_OUT voltages update with the appropriate bank

values based on a combination of LD and BKSEL

pins.

Figure 15. LD/BKSEL Function and DAC Output TIming Diagram

Table 5. BANK0 and BANK1 DAC Addresses

GAMMA BANK0 BANK1

BUFFER

OUTPUT REGISTER R4 R3 R2 R1 R0 REGISTER R4 R3 R2 R1 R0

OUT0 Register 0 BANK0 0 0 0 0 0 Register 0 BANK1 1 0 0 0 0

OUT1 Register 1 BANK0 0 0 0 0 1 Register 1 BANK1 1 0 0 0 1

OUT2 Register 2 BANK0 0 0 0 1 0 Register 2 BANK1 1 0 0 1 0

OUT3 Register 3 BANK0 0 0 0 1 1 Register 3 BANK1 1 0 0 1 1

OUT4 Register 4 BANK0 0 0 1 0 0 Register 4 BANK1 1 0 1 0 0

OUT5 Register 5 BANK0 0 0 1 0 1 Register 5 BANK1 1 0 1 0 1

OUT6 Register 6 BANK0 0 0 1 1 0 Register 6 BANK1 1 0 1 1 0

OUT7 Register 7 BANK0 0 0 1 1 1 Register 7 BANK1 1 0 1 1 1

OUT8 Register 8 BANK0 0 1 0 0 0 Register 8 BANK1 1 1 0 0 0

OUT9 Register 9 BANK0 0 1 0 0 1 Register 9 BANK1 1 1 0 0 1

OUT10 Register 10 BANK0 0 1 0 1 0 Register 10 BANK1 1 1 0 1 0

OUT11 Register 11 BANK0 0 1 0 1 1 Register 11 BANK1 1 1 0 1 1