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BKSEL

SCL

SDA

Control(IFandMemory)

OUT9

BUF12840

DACRegisterBank1

DACRegisterBank0

OUT0

OUT1

OUT10

OUT11

External

Memory

Control

EA1

EA0

BUF12840

www.ti.com

SBOS519A –OCTOBER 2010– REVISED JULY 2011

Programmable Gamma-Voltage Generator

with Integrated Two-Bank Memory and External EEPROM

FEATURES

DESCRIPTION

The BUF12840 offers 12 programmable gamma

• 10-BIT RESOLUTION

channels with external electrically erasable

• 12-CHANNEL P-GAMMA

programmable read-only memory (EEPROM) read

• READS FROM EXTERNAL EEPROM

capabilities.

• TWO INDEPENDENT PIN-SELECTABLE

The BUF12840 has two separate memory banks that

MEMORY BANKS

allow simultaneous storage of two different gamma

• RAIL-TO-RAIL OUTPUT:

curves to facilitate switching between gamma curves.

– 300mV Min Swing-to-Rail (10mA)

All gamma channels offer a rail-to-rail output that

– 200mV Min Swing-to-Rail (5mA)

typically swings to within 200mV of either supply rail

• LOW SUPPLY CURRENT

with a 5mA load. All channels are programmed using

• SUPPLY VOLTAGE: 9V to 20V

a two-wire interface that supports standard operations

up to 400kHz and high-speed data transfers up to

• DIGITAL SUPPLY: 2V to 5.5V

3.4MHz.

• TWO-WIRE INTERFACE: Supports 400kHz and

3.4MHz Operation

The BUF12840 is manufactured using Texas

Instruments’ proprietary, state-of-the-art, high-voltage

APPLICATIONS

CMOS process. This process offers very dense logic

and high supply voltage operation of up to 20V. The

• TFT-LCD REFERENCE DRIVERS

BUF12840 is offered in a QFN-24 package, and is

specified from –40°C to +95°C.

Summary of content (31 pages)

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BUF12840 SBOS519A – OCTOBER 2010 – REVISED JULY 2011 www.ti.com Programmable Gamma-Voltage Generator with Integrated Two-Bank Memory and External EEPROM FEATURES DESCRIPTION • • • • The BUF12840 offers 12 programmable gamma channels with external electrically erasable programmable read-only memory (EEPROM) read capabilities.
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BUF12840 SBOS519A – OCTOBER 2010 – REVISED JULY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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BUF12840 SBOS519A – OCTOBER 2010 – REVISED JULY 2011 www.ti.com ELECTRICAL CHARACTERISTICS Boldface limits apply over the specified temperature range, TA = –40°C to +95°C. At TA = +25°C, VS = +18V, and VSD = +5V, unless otherwise noted. BUF12840 PARAMETER CONDITIONS MIN TYP 17.7 17.
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BUF12840 SBOS519A – OCTOBER 2010 – REVISED JULY 2011 www.ti.com PIN CONFIGURATION OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 24 23 22 21 20 19 RGE PACKAGE 4mm × 4mm VQFN-24 (TOP VIEW) (1) OUT5 1 18 GNDD OUT4 2 17 BKSEL OUT3 3 16 A0 OUT2 4 15 SDA OUT1 5 14 SCL OUT0 6 13 LD 9 10 11 12 VSD EA1 EA0 EN 8 GNDA (1) VS 7 Exposed Thermal Pad (Bottom Side) NOTE: (1) GNDA and GNDD must be connected together. PIN DESCRIPTIONS 4 PIN NO.
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BUF12840 SBOS519A – OCTOBER 2010 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, VS = +18V, and VSD = +5V, unless otherwise noted. ANALOG SUPPLY CURRENT HISTOGRAM 1200 18 17.5 17 16.5 16 15.5 15 3 2.5 2 1.5 1 0.5 0 1000 Output Swing High Occurrence Output Voltage (V) OUTPUT VOLTAGE vs OUTPUT CURRENT (Channels 1–12) 800 600 400 Output Swing Low 200 0 0 25 50 75 100 125 5 150 5.5 6 6.5 7 7.5 8 Analog Supply Current (mA) Output Current (mA) Figure 1. Figure 2.
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BUF12840 SBOS519A – OCTOBER 2010 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = +18V, and VSD = +5V, unless otherwise noted. BKSEL SWITCHING TIME DELAY (LD Pin = 0) INTEGRAL LINEARITY ERROR 0.15 0.1 Error (LSB) BKSEL (2V/div) 0.05 7ms 0 18V -0.05 DAC Channel (9V/div) -0.1 0V -0.15 0 256 768 512 10ms/div 1024 Input Code Figure 7. Figure 8. Output Voltage (2V/div) LARGE-SIGNAL STEP RESPONSE Time (2ms/div) Figure 9.
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BUF12840 SBOS519A – OCTOBER 2010 – REVISED JULY 2011 www.ti.com APPLICATION INFORMATION GENERAL The BUF12840 programmable voltage reference allows fast and easy adjustment of 12 programmable gamma reference outputs, each with 10-bit resolution. The BUF12840 is programmed through a high-speed, two-wire interface. The final gamma values can be automatically loaded from an external EEPROM.
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BUF12840 SBOS519A – OCTOBER 2010 – REVISED JULY 2011 www.ti.com OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 0.1mF VS VS 1mF EA1 EA0 EN LD GNDD GNDA A0 A1 Power PAD SCL SDA EEPROM GNDD GNDD TCON 0.1mF 10kW SDA SCL BKSEL A0 VSD I/O I/O SDA SCL 0.1mF VSD 10kW Source Drivers BUF12840 VSD VSD Figure 10.
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BUF12840 SBOS519A – OCTOBER 2010 – REVISED JULY 2011 www.ti.com 10ms is updated at this moment. The entire DAC register D9-D0 Ackn D0 D1 D2 D3 D4 D5 D6 D7 Ackn D8 D9 D10 D11 D12 D13 D14 D15 = 1, all DAC outputs are updated when the current DAC register is updated. D15 Ackn R0 R1 R2 R3 R4 D5 D6 D7 Ackn W A0 A1 A0 A1 A2 A6 A6 SDA_In Device_Out A5 A4 A3 Device Address DAC_OUTPUT SCL Write single DAC register. R4-R0 specify DAC address.
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BUF12840 SBOS519A – OCTOBER 2010 – REVISED JULY 2011 www.ti.com EEPROM ADDRESS SELECT PINS EA0 and EA1 are used to select the proper EEPROM size. Table 4 shows the start and stop address to load each of the DAC registers. The state of the select pins must be set before the auto read function is activated. Enable Pin The status of EN at power-on reset (POR) determines the modes of operation of the BUF12840, as described in Table 3.
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BUF12840 SBOS519A – OCTOBER 2010 – REVISED JULY 2011 www.ti.com POWER-ON RESET (POR) AUTO READ FUNCTION Figure 14 depicts the BUF12840 POR Master Mode auto read function and timing. The BUF12840 makes the first attempt to read the external EEPROM 5ms after the POR (power-on reset) condition is met, as shown in Figure 13. Following the initial 5ms wait period, the BUF12840 queries the EEPROM with a digital word that includes an EEPROM address and acknowledge request.
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BUF12840 SBOS519A – OCTOBER 2010 – REVISED JULY 2011 www.ti.com POR Time = 0 5ms 1.5V POR Activates Master Mode EEPROM Address + Acknowledge ¼ Idle SDA 900ms 1ms 5ms EN (high, '1') should be enabled prior to a query pulse and before the 10th query attempt to remain in master mode.
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BUF12840 SBOS519A – OCTOBER 2010 – REVISED JULY 2011 www.ti.com READ AGAIN When the BUF12840 is in slave mode, a read again (RA) command can be issued to restart an EEPROM data download. The RA command follows this process: 1. Send the BUF12840 device address with write bit: 11101000 if A0 = 0 or 11101010 if A0 = 1; the BUF12840 acknowledges this byte. 2. Send register address 00011100; the BUF12840 acknowledges this byte. 3.
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BUF12840 SBOS519A – OCTOBER 2010 – REVISED JULY 2011 www.ti.com WRITE BOTH BANKS OF DAC REGISTERS In slave mode, writes to both banks are accomplished through the two-wire bus; there are different register address for the two banks. The BKSEL pin does not impact writing to each of the banks. Table 5 details the DAC addresses for each bank. DAC_OUT voltages update with the appropriate bank values based on a combination of LD and BKSEL pins.
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BUF12840 SBOS519A – OCTOBER 2010 – REVISED JULY 2011 www.ti.com TIMING DIAGRAMS Figure 16 describes the timing operations on the BUF12840. Parameters for Figure 16 are defined in Table 6. Bus definitions are: Bus Idle: Both SDA and SCL lines remain high. Start Data Transfer: A change in the state of the SDA line, from high to low, while the SCL line is high, defines a START condition. Each data transfer is initiated with a START condition, denoted as S in Figure 16.
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Figure 17. General-Call Reset Timing SDA SCL SDA SCL Start High-Speed Command Start General-Call Reset Command Address Byte = 00h Address Byte = 00001xxx (HS Master Code) Ackn Ackn Device enters high-speed mode at ACK clock pulse. Device exits high-speed mode with stop condition. No Ackn Device begins reset at arrow and is in reset until ACK clock pulse. Then the device acquires memory, etc., as it does at power-up.
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BUF12840 SBOS519A – OCTOBER 2010 – REVISED JULY 2011 www.ti.com DYNAMIC GAMMA CONTROL Dynamic gamma control is a technique used to improve the picture quality in LCD TV applications. The brightness in each picture frame is analyzed and the gamma curves are adjusted on a frame-by-frame basis. The gamma curves are typically updated during the short vertical blanking period in the video signal. Figure 19 shows a block diagram using the BUF12840 for dynamic gamma control.
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BUF12840 SBOS519A – OCTOBER 2010 – REVISED JULY 2011 READ/WRITE OPERATIONS The BUF12840 is able to read from a single DAC or multiple DACs, or write to the register of a single DAC, or multiple DACs in a single communication transaction. DAC addresses for BANK0 begin with 00000, which corresponds to Register 0, through 01011, which corresponds to Register 11. DAC addresses for BANK1 begin with 10000, which corresponds to Register 0, through 11011, which corresponds to Register 11; see Table 5.
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A6 A5 A5 Copyright © 2010–2011, Texas Instruments Incorporated A6 A6 SDA_In Start A5 A5 A4 A4 A3 A3 Device Address A2 A2 A1 A1 A0 A0 W W Write A4 A4 A2 A2 Ackn Ackn Ackn D7 D7 Write Operation A3 A3 Device Address A1 A1 W W Ackn Ackn Ackn D7 D7 Write Operation D6 D6 D6 D6 D5 D5 R4 R4 R3 R3 R2 R2 R1 R1 D5 D5 R0 R0 R3 R3 Ackn Ackn Ackn R4 R4 R0 R0 Ackn Ackn D14 D14 D14 D14 D13 D13 D12 D12 D11 D11 D13 D13 D12 D12 D11 D11 D1
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BUF12840 SBOS519A – OCTOBER 2010 – REVISED JULY 2011 The BUF12840 acknowledges each byte. To terminate communication, send a STOP or START condition on the bus. Only DACs that have received both bytes are updated. Reading To read the register of one DAC: 1. Send a START condition on the bus. 2. Send the device address and read/write bit = LOW. The BUF12840 acknowledges this byte. 3. Send a DAC address byte. Bits D7−D5 are unused and should be set to 0. Bits D4−D0 are the DAC address; see Table 5.
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A6 A3 Copyright © 2010–2011, Texas Instruments Incorporated A2 A2 A1 A1 A0 A0 W W Ackn Ackn Ackn D7 D7 Read operation. A6 A6 SDA_In Device_Out Start A5 A5 A4 A4 A3 A3 Device Address A2 A2 Read multiple DAC registers. R4-R0 specify DAC address. A3 Write A1 A1 D6 D6 A0 A0 D5 D5 W W Write R4 R4 R2 R2 Ackn Ackn Ackn D7 D7 Read operation. R3 R3 DAC address pointer. D7-D5 must be 000.
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BUF12840 SBOS519A – OCTOBER 2010 – REVISED JULY 2011 www.ti.com OUTPUT PROTECTION VS The BUF12840 output stages can safely source and sink the current levels indicated in Figure 1. However, there are other modes where precautions must be taken to prevent to the output stages from being damaged by excessive current flow. The outputs (OUT1 through OUT12) include electrostatic discharge (ESD) protection diodes, as shown in Figure 24.
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BUF12840 SBOS519A – OCTOBER 2010 – REVISED JULY 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (October, 2010) to Revision A • Page Corrected error in x-axis value for Figure 9 ..........................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 10-Feb-2014 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 10-Feb-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device BUF12840AIRGER Package Package Pins Type Drawing VQFN RGE 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 4.25 B0 (mm) K0 (mm) P1 (mm) 4.25 1.15 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 10-Feb-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BUF12840AIRGER VQFN RGE 24 3000 367.0 367.0 35.
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