Datasheet

bq78PL116
www.ti.com SLUSAB8B –OCTOBER 2010– REVISED FEBRUARY 2011
SMBus Characteristics
(1)
over free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IL
Input low voltage 0 0.8 V
V
IH
Input high voltage 2.1 5.5 V
V
OL
Output low voltage 350-µA sink current 0 0.4 V
C
L
Capacitance, each I/O pin 10 pF
SCLK nominal clock
f
SCL
T
A
= 25°C 10 100 100 kHz
frequency
V
BUS
5 V nominal 13.3 45.3
Pullup resistors for SCLK,
R
PU
(2)
kΩ
SDATA
V
BUS
3 V nominal 2.4 6.8
(1) SMBus timing and signals meet the SMBus 2.0 specification requirements under normal operating conditions. All signals are measured
with respect to PACK-negative.
(2) Pullups are typically implemented external to the battery pack and are selected to meet SMBus requirements.
PowerLAN Characteristics
(1)(2)(3)
over free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
C
L
Load capacitance SDI1, SDI3, SDO0, SDO2, P-LAN 100 pF
SDI1 0.8 VLDO1
V
IH
Input logic high V
SDI3 0.8 VLDO2
SDO0, SDO2 0.9 VLDO1
V
OH
Output logic high V
P-LAN 0.9 VLDO2
SDI1 0.2 VLDO1
V
IL
Input logic low V
SDI3 0.2 VLDO2
SDO0, SDO2 0.1 VLDO1
V
OL
Output logic low V
P-LAN 0.1 VLDO2
t
r(I)
Input rise time SDI1, SDI3 500 ns
t
f(I)
Input fall time SDI1, SDI3 500 ns
t
r(O)
Output rise time SDO0, SDO2, P-LAN 30 50 ns
t
f(O)
Output fall time SDO0, SDO2, P-LAN 30 50 ns
(1) Values specified by design and are over the full input voltage range and the maximum load capacitance.
(2) The SDI and SDO pins are ac-coupled from the cell circuits downstream and upstream, respectively. The limits specified here are the
voltage transitions which must occur within the SDI and SDO rise-and fall-time specifications.
(3) Coupling capacitor between PowerLAN pins is 1000 pF. This value is specified by design.
© 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): bq78PL116