Datasheet

FLASH
PRE
CHG
EFCID
EFCIC
SMBus
DSG
SMBCLK
SMBDAT
SPROT
CSBAT
CSPACK
GPIO
6
C
ELL 4
Voltage
Temp
Balance
V4
P4N
P4S
XT4
V3
P3N
P3S
XT3
V2
P2N
P2S
XT2
CE
LL 3
Voltage
Temp
Balance
C
ELL 2
Voltage
Temp
Balance
C
ELL 1
Voltage
Temp
Balance
2.5VLDO
VLDO1
Watchdog
Coulomb Counter CCBAT
CCPACKCurrent A/D
Core / CPU
Measure
I/O
Safety
SRAM
RSTN
Internal
Temperature
RISC
CPU
Internal
Oscillator
Reset
Logic
First-LevelSafety
and
FET Control
Second-Level
Safety
LED1–5,
LEDEN
B0320-02
PowerLAN
Communication
Link
P-LAN
V1
P1N
P1S
XT1
bq78PL114
www.ti.com ................................................................................................................................................ SLUS850B – SEPTEMBER 2008 – REVISED APRIL 2009
Figure 1. bq78PL114 Internal Block Diagram
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Product Folder Link(s): bq78PL114