Datasheet

bq77PL900
www.ti.com ...................................................................................................................................................... SLUS844B – JUNE 2008 – REVISED JANUARY 2009
TERMINAL FUNCTIONS (continued)
NAME PIN # DESCRIPTION
NC 2, 7, 43, No connect (not electrically connected)
45
PACK 47 PACK positive terminal and alternative power source
PMS 46 Determines CHG output state for zero-volt charge
SCLK 27 Open-drain bidirectional serial interface clock with an internal 10-k Ω pullup to V
LOG
SDATA 26 Open-drain bidirectional serial interface data with an internal 10-k Ω pullup to V
LOG
SRBGND 22 Current sense terminal (Connect Battery to cell ’ s GND)
SRPGND 23 Current-sense positive terminal when discharging relative to SRNGND, current-sense negative terminal when
charging relative to SRGND. (Connect to pack GND)
TIN 38 Temperature sensing input
TOUT 39 Thermistor bias current source
VC1 10 Sense voltage input terminal for most positive cell, balance current input for most positive cell, and battery stack
measurement input
VC2 11 Sense voltage input terminal for second-most positive cell, balance current input for second-most positive cell, and
return balance current for most positive cell
VC3 12 Sense voltage input terminal for third-most positive cell, balance current input for third-most positive cell, and
return balance current for second-most positive cell
VC4 13 Sense voltage input terminal for fourth-most positive cell, balance current input for fourth-most positive cell, and
return balance current for third-most positive cell
VC5 14 Sense voltage input terminal for fifth-most positive cell, balance current input for fifth-most positive cell, and return
balance current for fourth-most positive cell
VC6 15 Sense voltage input terminal for sixth-most positive cell, balance current input for sixth-most positive cell, and
return balance current for fifth-most positive cell
VC7 16 Sense voltage input terminal for seventh-most positive cell, balance current input for seventh-most positive cell,
and return balance current for sixth-most positive cell
VC8 17 Sense voltage input terminal for eighth-most positive cell, balance current input for eighth-most positive cell, and
return balance current for seventh-most positive cell
VC9 18 Sense voltage input terminal for ninth-most positive cell, balance current input for ninth-most positive cell, and
return balance current for eighth-most positive cell
VC10 19 Sense voltage input terminal for tenth-most positive cell, balance current input for tenth-most positive cell, and
return balance current for ninth-most positive cell
VC11 20 Sense voltage input terminal for most negative cell, return balance current for least positive cell
VLOG 32 Data I/O voltage set by connecting either VREG1 or VREG2
VOUT 31 Amplifier output for cell voltage measurement
VREG1 42 Integrated 5-V regulator output
VREG2 40 Integrated 3.3-V regulator output
XALERT 25 Open-drain output used to indicate status register change. (Includes an internal 100-k Ω pullup to V
LOG
.)
XRST 28 Power-on-reset output. Active-low open-drain output with an internal 3-k Ω pullup to V
LOG
ZEDE 36 Protection delay test pin. Minimizes protection delay times when connected to V
LOG
. Programmed delay times
used when pulled to GND, normal operation.
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