Datasheet

UV_CFG: Undervoltage Hysteresis and Threshold Configuration Register
bq77PL900
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...................................................................................................................................................... SLUS844B JUNE 2008 REVISED JANUARY 2009
UV LEVEL REGISTER (0x07)
7 6 5 4 3 2 1 0
0 UVFET _-DIS UVH1 UVH0 UV3 UV2 UV1 UV0
The UV register determines the cell undervoltage threshold, hysteresis voltage, and detection delay time.
UV_CFG b2 b0 (UV3 0) configuration bits with corresponding voltage threshold with a default of 000. Resolution
is 100 mV.
0x00 1.4 V 0x04 1.8 V 0x08 2.2 V 0x0c 2.6 V
0x01 1.5 V 0x05 1.9 V 0x09 2.3 V 0x0d 2.7 V
0x02 1.6 V 0x06 2 V 0x0a 2.4 V 0x0e 2.8 V
0x03 1.7 V 0x07 2.1 V 0x0b 2.5 V 0x0f 2.9 V
UV_CFG b5 b4 (UVH1 0) configuration bits with corresponding hysteresis voltage with a default of 00.
Resolution is 200 mV.
0x00 0.2 V 0x01 0.4 V 0x02 0.8 V 0x03 1.2 V
When the undervoltage threshold and the hysteresis values are high, then undervoltage recovery may not occur.
To avoid this, Table 12 should be used for assistance in configuration.
Table 12. Combination of UV Release Voltage vs Hysteresis
HYSTERESIS
0.2 V 0.4 V 0.8 V 1.2 V
1.4 1.6 1.8 2.2 2.6
1.5 1.7 1.9 2.3 2.7
1.6 1.8 2 2.4 2.8
1.7 1.9 2.1 2.5 2.9
1.8 2 2.2 2.6 3
1.9 2.1 2.3 2.7 3.1
2 2.2 2.4 2.8 3.2
2.1 2.3 2.5 2.9 3.3
Cell undervoltage (V)
2.2 2.4 2.6 3 3.3
2.3 2.5 2.7 3.1 3.3
2.4 2.6 2.8 3.2 3.3
2.5 2.7 2.9 3.3 3.3
2.6 2.8 3 3.3 3.3
2.7 2.9 3.1 3.3 3.3
2.8 3 3.2 3.3 3.3
2.9 3.1 3.3 3.3 3.3
UV_CFG b6 (UVFET_DIS): This bit disable automatically turns off the DSG output when UV is detected in
host-control mode.
0 = DSG output changes to OFF when UV is detected (default).
1 = DSG output does not change to OFF when UV is detected.
But the UV bit of the status register (0x00) is changed, even if this bit = 1.
UV_CFG b7: This bit should be set to 0, so that the bq77PL900 protects battery cell safety.
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