Datasheet

CELL_BALANCE: Cell (1 to 8) Balance Register
CELL_SEL: Cell Translation Selection and Cell Translation Status Register
bq77PL900
www.ti.com ...................................................................................................................................................... SLUS844B – JUNE 2008 – REVISED JANUARY 2009
CELL_BALANCE REGISTER (0x04)
7 6 5 4 3 2 1 0
CBAL8 CBAL7 CBAL6 CELL5 CBAL4 CBAL3 CBAL2 CBAL1
The CELL_BALANCE register controls cell balancing of the bq77PL900.
CELL_BALANCE b7(CBAL8): This bit enables VC3 – VC4 cell balance charge bypass path.
CELL_BALANCE b6(CBAL7): This bit enables VC4 – VC5 cell balance charge bypass path.
CELL_BALANCE b5(CBAL6): This bit enables VC5 – VC6 cell balance charge bypass path.
CELL_BALANCE b4(CBAL5): This bit enables VC6 – VC7 cell balance charge bypass path.
CELL_BALANCE b3(CBAL4): This bit enables VC7 – VC8 cell balance charge bypass path.
CELL_BALANCE b2(CBAL3): This bit enables VC8 – VC9 cell balance charge bypass path.
CELL_BALANCE b1(CBAL2): This bit enables VC9 – VC10 cell balance charge bypass path.
CELL_BALANCE b0(CBAL1): This bit enables VC10 – VC11 cell balance charge bypass path.
0 = Disable series cell balance charge bypass path (default).
1 = Enable series cell balance charge bypass path.
CELL_SEL REGISTER (0x05)
7 6 5 4 3 2 1 0
0 CAL2 CAL1 CAL0 CELL4 CELL3 CELL2 CELL1
The CELL_SEL register determines the cell selection for voltage measurement and translation. The register also
determines operation mode of the cell voltage monitoring.
The CELL_SEL b6 – b4 (CAL2 – CAL0) bits should be 0 when VAEN(b0) in register 3 is changed from 0 to 1 or the
VOUT pin will not go active.
This register is don ’ t care when either BAT(b4) or PACK(b3) is set or VAEN(b0) is cleared in register 3.
CELL_SEL b3 – b0 (CELL4 – 1): These four bits select the series cell for voltage measurement translation.
These are don ’ t care when CAL2 – 0 are not equal to 0x0.
CELL4 CELL3 CELL2 CELL1 SELECTED CELL
0 0 0 0 VC10 – VC11, Bottom series element (default)
0 0 0 1 VC9 – VC10, Second-lowest series element
0 0 1 0 VC8 – VC9, Third-lowest series element
0 0 1 1 VC7 – VC8, Fourth-lowest series element
0 1 0 0 VC6 – VC7, Fifth-lowest series element
0 1 0 1 VC5 – VC6, Sixth-highest series element
0 1 1 0 VC4 – VC5, Seventh-highest series element
0 1 1 1 VC3 – VC4, Eighth-highest series element
1 0 0 0 VC2 – VC3, Ninth-highest series element
1 0 0 1 VC1 – VC2, Top series element
Other VC10 – VC11, Bottom series element
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