Datasheet

OUTPUT_CONTROL: Output Control Register
bq77PL900
SLUS844B – JUNE 2008 – REVISED JANUARY 2009 ...................................................................................................................................................... www.ti.com
OUTPUT_CONTROL REGISTER (0x01)
7 6 5 4 3 2 1 0
FS PFALT 0 0 GPOD CHG DSG LTCLR
The OUPTUT_CONTROL register controls some of the outputs of the bq77PL900 and can show the state of the
external pin corresponding to the control.
OUTPUT_ CONTROL b0 (LTCLR): When a fault is latched, this bit releases the fault latch when toggled
(default).
0 → 1 → 0 clears the fault latches, allowing STATUS to be cleared on its next read.
OUTPUT_ CONTROL b1 (DSG): This bit controls the external discharge FET.
0 = Discharge FET is OFF in host-control mode.
1 = Discharge FET is ON in host-control mode.
OUTPUT_ CONTROL b2 (CHG): This bit controls the external charge FET.
0 = Charge FET is OFF in host-control mode.
1 = Charge FET is ON in host-control mode.
OUTPUT_CONTROL b3 (GPOD): This bit enables or disables the GPOD output.
0 = GPOD output is high impedance (default).
1 = GPOD output is active (GND).
OUTPUT_CONTROL b6 (PFALT): This bit indicates a parity error in the EEPROM. This bit is read-only.
0 = No parity error (default)
1 = A parity error has occurred.
OUTPUT_CONTROL b7 (FS): This bit selects the undervoltage detection sampling time.
0 = Sampling time is 50 ms/cell (typ) (default).
1 = Sampling time is 100 µ s/cell (typ)
OUTPUT_CONTROL b6-b4: These bits are not used and should be set to 0.
42 Submit Documentation Feedback Copyright © 2008 – 2009, Texas Instruments Incorporated
Product Folder Link(s): bq77PL900