Datasheet

Alerting the Host (LTCLR)
FET Control AccessbyHost
FaultFlagSet
LTCLRBit
XALERT Output
Fault Timeout
Expired
STATUSRegister
Read
T0376-01
POR
REGOutput
XRST Output
VREGTH+
VREGTH–
VLOG
t
RST
T0377-01
bq77PL900
www.ti.com ...................................................................................................................................................... SLUS844B – JUNE 2008 – REVISED JANUARY 2009
In host-control mode, when a protection fault occurs, the state is latched. The fault flag is unlatched by toggling
(from 0, set to 1 then reset to 0) OUTPUT_CONTROL [LTCLR]. The OCD, SCD, OV, and UV bits are unlatched
by this function. Now the FETs can be controlled by programming the OUTPUT_CONTROL register, and the
XALERT output can be cleared by reading the STATUS register. When detecting overvoltage or undervoltage
faults, LTCTR changes are ignored. After a period of 1 ms, it must send an LTCLR command.
Figure 21. LTCLR and XLAERT Clear Timing (Host-Control Mode)
The XRST open-drain output pin is triggered on activation of the VREG1 or VREG2 output. This holds the host
controller in reset for t
RST
, allowing V
VREG1
or V
VREG2
to stabilize before the host controller is released from reset.
The XRST output and monitoring voltage is supplied by the source of VLOG. When VLOG is connected to
VREG1, the XRST output level is V
VREG1
and monitors the activation of VREG1. When VLOG is connected to
VREG2, the XRST output level is V
VREG2
and monitors the activation of VREG2.
When V
VREG1
or V
VREG2
voltage is below the output specifications, XRST is active-low (0.8 × VLOG). When V
BAT
is below 7 V, VREG1 and VREG2 stop, then XRST goes low. If a host has a problem with a sudden reset signal,
it is recommended monitoring the battery voltage to avoid it, e.g., burnout detection.
Figure 22. XRST Timing Chart – Power Up and Power Down
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