Datasheet
Series Configuration of Five to Ten Cells
Delay Time Zero
Cell Voltage Measurement
Cell Voltage Measurement Calibration
bq77PL900
SLUS844B – JUNE 2008 – REVISED JANUARY 2009 ......................................................................................................................................................
www.ti.com
Unused cell inputs are required to be shorted to the uppermost-voltage-connected terminal. For example, in a
five-cell configuration, VC1 to VC5 are shorted to VC6. In a 9-cell configuration, VC1 is shorted to VC2.
The CNF0, CNF1, and CNF2 pins should be connected to VLOG = logic 1 (through a10-k Ω resistance) or GND =
logic 0 (directly) according to the desired cell configuration as seen in Table 7 .
Table 7. Cell Configuration
CELL
CNF2 PIN CNF1 PIN CNF0 PIN
CONFIGURATION
0 0 0 10-cell
0 0 1 9-cell
0 1 0 8-cell
0 1 1 7-cell
1 0 0 6-cell
1 0 1 5-cell
All other combinations 10-cell
The ZEDE pin enables EEPROM-programmed detection delay times when connected with GND (normal
operation). The detection delay time is set to 0 when this pin is connected with VLOG. This is typically used in
battery manufacturing test only.
The cell voltage is translated to allow a host controller to measure individual series elements of the battery. The
series element voltage is presented on the VOUT terminal. The cell voltage amplifier gain can be selected as
one of the following two equations. The VOUT voltage gain is selected by STATE_CONTROL [VGAIN]. VOUT is
internally connected to ground when disabled.
V
OUT
1 = 0.975 – {(Cell voltage) × 0.15} when VGAIN = 0
or
V
OUT
2 = 1.2 – {(Cell voltage) × 0.20} when VGAIN = 1
The total pack voltage can also be monitored. The PACK voltage output is enabled or disabled by
FUNCTION_CONTROL [PACK].
V
OUT
3 = (Total pack voltage) × 0.02 when PACK = 1
The total pack voltage can also be monitored. The BAT voltage output is enabled or disabled by
FUNCTION_CONTROL [BAT].
V
OUT
4 = (Total battery voltage) × 0.02 when BAT = 1
The bq77PL900 cell-voltage monitor consists of a sample-and-hold (S/H) circuit and differential amplifier.
30 Submit Documentation Feedback Copyright © 2008 – 2009, Texas Instruments Incorporated
Product Folder Link(s): bq77PL900