Datasheet

bq76PL536A-Q1
SLUSAM3 – MAY 2011 www.ti.com
Changes and Enhancements From bq76PL536
• Improved power management during CRC faults – Configuration bit IO_CONFIG[CRCNOFLT] (bit7) was
added to disable CRC fault from asserting the FAULT pin. This feature is useful under very low-power
operating conditions.
• ADC accuracy improvements – The conversion timing is now fixed at 6µs, offering improved accuracy over
the original bq76PL536.
• Improved ADC automatic mode functionality, allowing optimized and fully automatic internal power
management (ADC_CTRL[ADC_ON]=0) during normal operation at sample rates (time between conversions)
> 10 ms.
• Pin DRDY logic now indicates conversion status of all devices in the system.
• Improved V
BUS
communications reduce noise, enhance drive levels and hysteresis to improve battery stack
communications, and eliminate eight external components or more. Support for longer distances between ICs
and/or higher speeds for implementing large battery stack sizes.
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Product Folder Link(s): bq76PL536A-Q1