Datasheet

bq76PL536A
SLUSAD3A –JUNE 2011–REVISED AUGUST 2012 www.ti.com
HOST INTERFACE
Typical values stated where T
A
= 25°C and V
BAT
= 20 V, Min/Max values stated where T
A
= –40°C to 85°C and V
BAT
= 7.2 V
to 27 V (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
Logic-level output voltage, high; SDO_H, FAULT_H,
V
OH
C
L
= 20 pF, I
OH
< 5 mA
(1)
4.5 V
LDOD
V
ALERT_H, DRDY
Logic-level output voltage, low; SDO_H, FAULT_H,
V
OL
C
L
= 20 pF, I
OL
< 5 mA
(1)
VSS 0.5 V
ALERT_H, DRDY
Logic-level input voltage, high; SCLK_H, SDI_H, CS_H,
V
IH
2 5.2 V
CONV
Logic-level input voltage, low; SCLK_H, SDI_H, CS_H,
V
IL
VSS 0.8 V
CONV
C
IN
Input capacitance SCLK_H, SDI_H, CS_H, CONV 5 pF
I
LKG
Input leakage current SCLK_H, SDI_H, CS_H, CONV 1 µA
(1) Total simultaneous current drawn from all pins is limited by LDOD current to ≤10 mA.
GENERAL PURPOSE INPUT/OUTPUT (GPIO)
Typical values stated where T
A
= 25°C and V
BAT
= 20 V, Min/Max values stated where T
A
= –40°C to 85°C and V
BAT
= 7.2 V
to 27 V (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
V
IH
Logic-level input voltage, high Vin ≤ V
REG50
2 V
V
IL
Logic-level input voltage, low 0.8 V
V
OH
Output high-voltage pullup voltage Supplied by external ~100-kΩ resistor V
REG50
V
V
OL
Logic-level output voltage, low I
OL
= 1 mA 0.3 V
C
IN
Input capacitance(1) 5 pF
I
LKG
Input leakage current 1 µA
CELL BALANCING CONTROL OUTPUT (CBx)
Typical values stated where T
A
= 25°C and V
BAT
= 20 V, Min/Max values stated where T
A
= –40°C to 85°C and V
BAT
= 7.2 V
to 27 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CB
z
Output impedance 1 V < V
CELL
< 5 V 80 100 120 kΩ
V
RANGE
Output V V
Cn-1
V
Cn
V
ANALOG-TO-DIGITAL CONVERTER
ADC Common Specifications
Typical values stated where T
A
= 25°C and V
BAT
= 20 V, Min/Max values stated where T
A
= –40°C to 85°C and V
BAT
= 7.2 V
to 27 V (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
ADC_CONTROL[ADC_ON] = 1 5.4 6 6.6 µs
t
CONV_START
CONV high to conversion start
(1) (2)
ADC_CONTROL[ADC_ON] = 0 500 µs
ADC_CONTROL[ADC_ON] = 1
t
CONV
Conversion time per selected channel
(3)(4)
5.4 6 6.6 µs
FUNCTION_CONFG[ADCTx]=00
I
LKG
Input leakage current Not converting <10 100 nA
(1) If ADC_CONTROL[ADC_ON] = 0, add 500 µs to conversion time to allow ADC subsystem to stabilize. This is self-timed by the part.
(2) Additional 50 ms (POR) is required before first conversion after a) initial cell connection; or b) V
BAT
falls below V
POR
.
(3) ADC specifications valid when device is programmed for 6-µs conversion time per channel, FUNC_CONFIG[ADCT1:0] = 01b.
(4) Plus t
CONV_START
, i.e., if device is programmed for six channel conversions, total time is approximately 6 × 6 + 6 = 42 µs.
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