Datasheet

bq76PL536A

SLUSAD3A –JUNE 2011–REVISED AUGUST 2012

www.ti.com

Changes and Enhancements for bq76PL536A

• Improved power management during CRC faults – Configuration bit IO_CONFIG[CRCNOFLT] (bit7) was

added to disable CRC fault from asserting the FAULT pin. This feature is useful under very low-power

operating conditions.

• ADC accuracy improvements – The conversion timing is now fixed at 6 µs, offering improved accuracy over

the original bq76PL536.

• Improved ADC automatic mode functionality, allowing optimized and fully automatic internal power

management (ADC_CTRL[ADC_ON] = 0) during normal operation at sample rates (time between

conversions) > 10 ms.

• Pin DRDY logic now indicates conversion status of all devices in the system.

• Improved V

BUS

communications reduce noise, enhance drive levels and hysteresis to improve battery stack

communications, and eliminate eight external components or more. Support for longer distances between ICs

and/or higher speeds for implementing large battery stack sizes.

• Improved flowchart for device addressing provided in data sheet.

Spacer

REVISION HISTORY

Changes from Revision Original (June 2011) to Revision A Page

• Changed the pinout image to remove the device number and package type ...................................................................... 4

Product Folder Links :bq76PL536A