Datasheet
5V LDO
(User Circuitry)
VC2
REG50
GPAI–
GPAI+
GPIO
AUX
14 bit
ADC
VC1
VC3
VC4
VC5
VC6
CB2
CB1
CB3
CB4
CB5
CB6
LDO-A LDO-D
LDOA
LDOD
VC0
REF2
OV
UV
OV
UV
OV
UV
OV
UV
OV
UV
OV
UV
CELL BALANCING
+
-
TS1–
TS1+
TS2–
TS2+
OT1
OT2
VBAT
V
REF
2.5V
ULTRA-PRECISION
BANDGAP
VREF
FAULT _S
SCLK_S
SDI_S
SDO_S
CS_S
ALERT_S
CONV_S
DRDY_S
FAULT _N
SCLK_N
SDI_N
SDO_N
CS_N
ALERT_N
CONV_N
DRDY_N
FAULT _H
SCLK_H
SDI_H
SDO_H
CS_H
ALERT_H
CONV_H
DRDY_H
THERMAL
SHUTDOWN
bq76PL536
1.25V REF2
AGND
HOST
INTERFACE
DIGITAL
CONTROL
LOGIC
REGISTERS
EPROM
OSC
SHIFTED
NORTH
COMM’s
INTERFACE
LEVEL
SHIFTED
SOUTH
COMM’s
INTERFACE
LEVEL SHIFT AND MUX
ANALOG
COMMUNICATIONS
POWER
DIGITAL
PROTECTOR
VSS
VSSD
VSS
bq76PL536A
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SLUSAD3A –JUNE 2011–REVISED AUGUST 2012
FUNCTIONAL BLOCK DIAGRAM
Figure 2. bq76PL536A Block Diagram
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