Datasheet

bq76PL536A
SLUSAD3A –JUNE 2011–REVISED AUGUST 2012 www.ti.com
CB_TIME REGISTER (0x33)
7 6 5 4 3 2 1 0
CBT[7] – CBT[5] CBT[4] CBT[3] CBT[2] CBT[1] CBT[0]
The CB_TIME register sets the maximum high (active) time for the cell balance outputs from 0 seconds to 63
minutes. When set to 0, no balancing can occur – balancing is effectively disabled.
[7] Controls minutes/seconds counting resolution.
0 = Seconds (default)
1 = Minutes
[5..0] Sets the time duration as scaled by CBT.7
ADC_CONVERT REGISTER (0x34)
7 6 5 4 3 2 1 0
– – – – – – – CONV
The CONVERT_CTRL register is used to start conversions.
[0] (CONV): This bit starts a conversion, using the settings programmed into the ADC_CONTROL[]
register. It provides a programmatic method of initiating conversions.
0 = No conversion (default)
1 = Initiate conversion. This bit is automatically reset after conversion begins, and always
returns 0 on READ.
SHDW_CTRL REGISTER (0x3a)
7 6 5 4 3 2 1 0
SHDW[7] SHDW[6] SHDW[5] SHDW[4] SHDW[3] SHDW[2] SHDW[1] SHDW[0]
The SHDW_CTRL register controls writing to Group3 protected registers. Default at RESET = 0x00.
The value 0x35 must be written to this register to allow writing to Group3 protected registers in the range
0x40–0x4f. The register always returns 0x00 on read. The register is reset to 0x00 after any successful write,
including a write to non-Group3 registers. A read operation does not reset this register.
Writing the value 0x27 results in all Group3 protected registers being refreshed from OTP programmed values.
The register is reset to 0x00 after the REFRESH is complete.
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