Datasheet

bq76PL536A

www.ti.com

SLUSAD3A –JUNE 2011–REVISED AUGUST 2012

IO_CONTROL REGISTER (0x31)

7 6 5 4 3 2 1 0

AUX GIPI_OUT GPIO_IN 0 0 SLEEP TS2 TS1

The IO_CONTROL register controls some features of the bq76PL536A external I/O pins.

[7] (AUX): Controls the state of the AUX output pin, which is internally connected to REG50.

0 = Open

1 = Connected to REG50

[6] (GPIO_OUT): Controls the state of the open-drain GPIO output pin; the pin should be programmed to 1

to use the GPIO pin as an input.

0 = Output low

1 = Open-drain

[5] (GPIO_IN): Represents the input state of GPIO pin when used as an input

0 = GPIO input is low.

1 = GPIO input is high.

[4] Not implemented. Must be written as 0.

[3] Not implemented. Must be written as 0.

[2] (SLEEP): Places the device in a low-quiescent-current state. All CUV, COV, and OT comparators

are disabled. A 1-ms delay to stabilize the reference voltage is required to exit SLEEP

mode and return to active COV, CUV monitoring.

0 = ACTIVE mode

1 = SLEEP mode

[1..0] (TSx) Controls the connection of the TS1(2) inputs to the ADC VSS connection point. When set,

the TSx(–) input is connected to VSS. These bits should be set to 0 to reduce the current

draw of the system.

0 = Not connected

1 = Connected

CB_CTRL REGISTER (0x32)

7 6 5 4 3 2 1 0

– – CBAL[6] CBAL[5] CBAL[4] CBAL[3] CBAL[2] CBAL[1]

The CB_CTRL register determines the internal cell balance output state.

CB_CTRL b(n = 5 to 0) (CBAL(n + 1)): This bit determines if the CB(n) output is high or low.

0 = CB[n] output is low (default).

1 = CB[n] output is high (active).

Product Folder Links :bq76PL536A