Datasheet
bq76PL536A
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SLUSAD3A –JUNE 2011–REVISED AUGUST 2012
GPAI (0x01, 0x02)
15 14 13 12 11 10 9 8
GPAI[15] GPAI [14] GPAI [13] GPAI [12] GPAI [11] GPAI [10] GPAI [9] GPAI [8]
7 6 5 4 3 2 1 0
GPAI [7] GPAI [6] GPAI [5] GPAI [4] GPAI [3] GPAI [2] GPAI [1] GPAI [0]
The GPAI register reports the ADC measurement of GPAI+/GPAI– in units of LSBs.
Bits 15–8 are returned at address 0x01, bits 7–0 at address 0x02.
VCELLn REGISTER (0x03…0x0e)
15 14 13 12 11 10 9 8
VCELLn[15] VCELLn[14] VCELLn[13] VCELLn[12] VCELLn[11] VCELLn[10] VCELLn[9] VCELLn[8]
7 6 5 4 3 2 1 0
VCELLn[7] VCELLn[6] VCELLn[5] VCELLn[4] VCELLn[3] VCELLn[2] VCELLn[1] VCELLn[0]
The VCELLn registers report the converted data for cell n, where n = 1 to 6.
Bits 15–8 are returned at odd addresses (e.g. 0x03), bits 7–0 at even addresses (e.g. 0x04).
TEMPERATURE1 REGISTER (0x0f, 0x10)
15 14 13 12 11 10 9 8
TEMP1[15] TEMP1[14] TEMP1[13] TEMP1[12] TEMP1[11] TEMP1[10] TEMP1[9] TEMP1[8]
7 6 5 4 3 2 1 0
TEMP1[7] TEMP1[6] TEMP1[5] TEMP1[4] TEMP1[3] TEMP1[2] TEMP1[1] TEMP1[0]
The TEMPERATURE1 register reports the converted data for TS1+ to TS1–.
Bits 15–8 are returned at odd addresses (e.g., 0x0f), bits 7–0 at even addresses (e.g., 0x10).
TEMPERATURE2 REGISTER (0x11, 0x12)
15 14 13 12 11 10 9 8
TEMP2[15] TEMP2[14] TEMP2[13] TEMP2[12] TEMP2[11] TEMP2[10] TEMP2[9] TEMP2[8]
7 6 5 4 3 2 1 0
TEMP2[7] TEMP2[6] TEMP2[5] TEMP2[4] TEMP2[3] TEMP2[2] TEMP2[1] TEMP2[0]
The TEMPERATURE2 register reports the converted data for TS2+ to TS2–.
Bits 15–8 are returned at odd addresses (e.g., 0x11), bits 7–0 at even addresses (e.g., 0x12).
ALERT_STATUS REGISTER (0x20)
7 6 5 4 3 2 1 0
AR PARITY ECC_ERR FORCE TSD SLEEP OT2 OT1
The ALERT_STATUS register provides information about the source of the ALERT signal. The host must clear
each alert flag by writing a 1 to the bit that is set. The exception is bit 4, which may be written 1 or 0 as needed
to implement self-test of the IC stack and wiring.
[7] AR This bit indicates that the ADDR[0]…[5] bits have been written to a valid address. This bit
is an inverted copy of the ADDRESS_CONTROL[AR] bit. It is not cleared until an
address has been programmed in ADDRESS_CONTROL and a 1 followed by a 0 (two
writes) is written to the bit.
0 = Address has been assigned.
1 = Address has not been assigned (default at RESET).
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