Datasheet

bq76PL536A
SLUSAD3A –JUNE 2011–REVISED AUGUST 2012 www.ti.com
When a double-bit (uncorrectable) error is found, DEVICE_STATUS[ALERT] is set, the ALERT_S (ALERT_H for
bottom stack device) line is activated, and the ALERT_STATUS[] register returns the ECC_ERR and/or I_FAULT
bit = 1(true). The device may return erroneous measurement data, and/or fail to detect COV, CUV, or OT faults
in this state.
EPROM bits are shipped from the factory set to 0, and must be programmed to the 1 state as required.
Table 3. Data and Control Register Descriptions
NAME ADDR GROUP ACCESS
(1)
RESET DESCRIPTION
DEVICE_STATUS 0x00 1 R 0 Status register
GPAI 0x01, 0x02 1 R 0 GPAI measurement data
VCELL1 0x03, 0x04 1 R 0 Cell 1 voltage data
VCELL2 0x05, 0x06 1 R 0 Cell 2 voltage data
VCELL3 0x07, 0x08 1 R 0 Cell 3 voltage data
VCELL4 0x09, 0x0a 1 R 0 Cell 4 voltage data
VCELL5 0x0b, 0x0c 1 R 0 Cell 5 voltage data
VCELL6 0x0d, 0x0e 1 R 0 Cell 6 voltage data
TEMPERATURE1 0x0f, 0x10 1 R 0 TS1+ to TS1– differential voltage data
TEMPERATURE2 0x11, 0x12 1 R 0 TS2+ to TS2– differential voltage data
RSVD 0x13–0x1f – – – Reserved for future use
ALERT_STATUS 0x20 2 R/W 0x80 Indicates source of ALERT signal
FAULT_STATUS 0x21 2 R/W 0x08 Indicates source of FAULT signal
COV_FAULT 0x22 1 R 0 Indicates cell in OV fault state
CUV_FAULT 0x23 1 R 0 Indicates cell in UV fault state
PRESULT_A 0x24 1 R 0 Parity result of Group3 protected registers (A)
PRESULT_B 0x25 1 R 0 Parity result of Group3 protected registers (B)
RSVD 0x26–0x2f – – – Reserved for future use
ADC_CONTROL 0x30 2 R/W 0 ADC measurement control
IO_CONTROL 0x31 2 R/W 0 I/O pin control
CB_CTRL 0x32 2 R/W 0 Controls the state of the cell-balancing outputs CBx
CB_TIME 0x33 2 R/W 0 Configures the CB control FETs maximum on time
ADC_CONVERT 0x34 2 R/W 0 ADC conversion start
RSVD 0x35–0x39 – – – Reserved for future use
SHDW_CTRL 0x3a 2 R/W 0 Controls WRITE access to Group3 registers
ADDRESS_CONTROL 0x3b 2 R/W 0 Address register
RESET 0x3c 2 W 0 RESET control register
TEST_SELECT 0x3d 2 R/W 0 Test mode selection register
RSVD 0x3e – – – Reserved for future use
E_EN 0x3f 2 R/W 0 EPROM programming mode enable
FUNCTION_CONFIG 0x40 3 R/W EPROM Default configuration of device
IO_CONFIG 0x41 3 R/W EPROM I/O pin configuration
CONFIG_COV 0x42 3 R/W EPROM Overvoltage set point
CONFIG_COVT 0x43 3 R/W EPROM Overvoltage time-delay filter
CONFIG_CUV 0x44 3 R/W EPROM Undervoltage setpoint
CONFIG_CUVT 0x45 3 R/W EPROM Undervoltage time-delay filter
CONFIG_OT 0x46 3 R/W EPROM Overtemperature set point
CONFIG_OTT 0x47 3 R/W EPROM Overtemperature time-delay filter
USER1 0x48 3 R EPROM User data register 1, not used by device
USER2 0x49 3 R EPROM User data register 2, not used by device
USER3 0x4a 3 R EPROM User data register 3, not used by device
(1) Key: R = Read; W = Write
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