Datasheet
REGISTER
7
CRC_ERR
WRITE
6 5 4 3 2 1 0
INTERNAL DATA BUS
CONTROL, STATUS & DATA REGISTERS
FAULT _STATUSFLAGS
CRCCHECKLOGIC
SPIDE -SERIALIZER
bq76PL536A
SLUSAD3A –JUNE 2011–REVISED AUGUST 2012
www.ti.com
Once the address is written, the ADDRESS_CONTROL[AR] bit is set which is copied to the
DEVICE_STATUS[AR] and also ALERT_S if ALERT_N is also de-asserted. This allows the CS_N pin to follow
(asserted) the CS_S pin assertions. The process of addressing can now be repeated as device ‘n’ has a new
address and device n+1 has the default address of 0x00, and can be changed to its correct address in the stack.
If a device loses its address through a POR or it is replaced then this device will be the highest logical device in
the stack able to be addressed (0x00) as its CS_N will be disabled and the addressing process is required to be
undertaken for this, and higher devices.
REGISTER ARCHITECTURE
I/O Register Details
The bq76PL536A has 48 addressable I/O registers. These registers provide status, control, and configuration
information for the battery protection system. Reserved registers return 0x00. Unused registers should not be
written to; the results are undefined. Unused or undefined bits should be written as zeros, and will always read
back as zeros. Several types of registers are provided, detailed as follows.
Register Types
Read-Only (Group 1)
These registers contain the results of conversions, or device status information set by internal logic. The contents
are re-initialized by a device reset as a result of either POR or the RESET command. Contents of the register are
changed by either a conversion command, or when there is an internal state change (i.e., a fault condition is
sensed).
Read / Write (Group 2)
This register group modifies the operations or behavior of the device, or indicates detailed status in the
ALERT_STATUS[] and FAULT_STATUS[] registers. The contents are re-initialized by a device reset as a result
of either POR or the RESET command. Contents of the register are changed either by a conversion command,
or when there is an internal state change (i.e., a fault condition is sensed).
Contents may also be changed by a write from the host CPU to the register. Writes may only modify a single
register at a time. If CRCs are enabled, the write packet is buffered until the CRC is checked for correctness.
Packets with bad CRCs are discarded without writing the value to the register, after setting the
FAULT_STATUS[CRC] flag.
Unused or undefined bits in any register should be written as zeros, and will always read back as zeros.
Figure 14. Register Group2 Architecture
32 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links :bq76PL536A