Datasheet

Reg Address
0 Device Address
1
RegData
CRC
R/W
WritePacket
CS Assertion
bq76PL536A
www.ti.com SLUSAD3A –JUNE 2011–REVISED AUGUST 2012
Figure 12. WRITE Packet Detail
Broadcast Writes
The bq76PL536A supports broadcasting single register writes to all devices. A write to device address 0x3f is
recognized by all devices on the bus with a valid address, and permits efficient simultaneous configuration of all
registers in the stack of devices. This also permits synchronizing all ADC conversions by a firmware command
sent to the CONVERT_CTRL[] register as an alternative to using the CONV and DRDY pins.
Communications Packet Structure
The bq76PL536A has two primary communication modes via the SPI interface. These two modes enable single-
byte read / write and multiple data reads. All writes are single-byte; the logical address is shifted one bit left, and
the LSB = 1 for writing.
All transactions are in the form of packets comprising:
BYTE DESCRIPTION
#1 6-bit bq76PL536A slave address + R/W bit 0b0xxx xxxW
#2 Starting data-register offset
#3 Number of data bytes to be read (n) (omitted for writes)
#4 to 3+n Data bytes
#4+n CRC (omit if IO_CONFIG[CRC_DIS] = 1)
CRC Algorithm
The cyclic redundancy check (CRC) is a CRC-8 error-checking byte, calculated on all the message bytes
(including addresses). It is identical in structure to the SMBus 2.0 packet error check (PEC), and is also known
as the ATM-8 CRC. The CRC is appended to the message for all SPI packets by the device that supplied the
data as the last byte in the packet (when IO_CONTROL[CRC] == 1).
Each bus transaction requires a CRC calculation by both the transmitter and receiver within each packet. The
CRC is calculated in a way that conforms to the polynomial, C(x) = x
8
+ x
2
+ x
1
+ 1 and must be calculated in the
order of the bits as received, MSB first. The CRC calculation includes all bytes in the transmission, including
address, command, and data. When reading data from the device, the CRC is based on the ADDRESS +
FIRST_REGISTER + LENGTH + returned_device_data[n]. The stuff-bytes used to clock out the data from the IC
are not used as part of the calculation, although if the value 0x00 is used, the 0s have no effect on the CRC.
CRC verification is performed by the receiver when the CS_x line goes false, indicating the end of a packet. If
the CRC verification fails, the message is ignored (discarded), the CRC failure flag is set in the
FAULT_STATUS[CRC] register, and the FAULT line becomes asserted and latched until the error is read and
cleared by the host.
The CRC bit returned in the FAULT_STATUS[] register reflects the last packet received, not the CRC condition
of the packet reading the FAULT_STATUS contents. CRC errors should be handled at a high priority by the host
controller, before writing to additional registers.
Data Packet Usage Examples
The bq76PL536Acan be enabled via the host to read just the specific voltage data which would require a total of
2 written bytes (chip address and R/W [#1] + first (starting) register offset [#2]) + LENGTH [#3] and 13 <null>
stuff bytes (12 [n] data bytes + CRC).
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