Datasheet

DEV ADDR
CS
1 byte
time
REG ADDR WRT DATA CRC DEV ADDR REG ADDR
Startofnextpacket
SDI
...
StartReg Address
0 Device Address
0
ReadLengthn
ReadData 1
R/W
ReadDatan
CRC
ReadPacket
CS Assertion
DEV ADDR
1 byte
time
REG ADDR CNT = n 0x00 0x00 0x00 0x00
READn... CRCREAD 1 READ 2
n + 1 placeholderbytes
CS
SDI
SDO
0x00 0x000x00
bq76PL536A
SLUSAD3A –JUNE 2011–REVISED AUGUST 2012 www.ti.com
Packet Formats
Data Read Packet
When the bq76PL536A is selected (CS_S [CS_H for first device] is active and the bq76PL536A has been
addressed) and read request has been initiated, then the data is transmitted on the SDO_S pin to the SDO_N
pin of the next device down the stack. This continues to the first device in the stack, where the data in from the
SDO_N pin is transmitted to the host via the SDO_H pin. The device supplying the read data generates a CRC
as the last byte sent.
Figure 9. READ Packet Format
Figure 10. READ Packet Detail
Data Write Packet
When the bq76PL536A is selected (CS_S is active and the bq76PL536A has been addressed) and a write
request has been initiated, the bq76PL536A receives data through the SDI_S pin, which is connected to the
SDO_N of the lower device. For the first device in the stack, the data is input to the SDI_H pin from the host, and
transmitted up the stack on the SDI_S pin to the SDI_N pin of the next higher device. If enabled, the device
checks the CRC, which it expects as the last byte sent. If the CRC is valid, no action is taken. If the CRC is
invalid or missing, the device asserts the ALERT_S signal to the next lower device, which ripples down the stack
to the ALERT_H pin on the lowest device. The host should then take action to clear the condition.
Unused or undefined register bits should be written as zeros.
Figure 11. WRITE Packet Format
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