Datasheet

ALERT
FAULT
DRDY
SPI
DRDY
FAULT
ALERT
SPI
PACK-
PACK+
HOST
INTERFACE
GPAI
GPIO
AUX
REG50
SPI
(North)
HOS T I N TE R F AC E
CONV
CONV
CBx (6)
CONTROL (North)
CELL_1
CELL_6
••• CELL_2-5 •••
ALERT
FAULT
DRDY
SPI
GPAI
GPIO
AUX
SPI
(North)
HOS T I N TE R F AC E
(not u s e d )
CONV
CBx (6)
CONTROL (North)
bq76PL536A
CELL_1
CELL_6
••• CELL_2-5 •••
TO NEXT DEVICE
CONTROL (South)
SPI
(South)
South Interface
(not used on bottom device)
bq76PL536A
bq76PL536A
SLUSAD3A –JUNE 2011–REVISED AUGUST 2012 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TYPICAL IMPLEMENTATION
Figure 1. Simplified System Connection
PIN DETAILS
PIN FUNCTIONS
PIN
TYPE
(1)
DESCRIPTION
NAME NO.
AGND 15 AI Internal analog V
REF (–)
ALERT_H 38 O Host-to-device interface – ALERT condition detected in this or higher (North) device
ALERT_N 57 I Current-mode input indicating a system status change from the next-higher bq76PL536A
ALERT_S 23 OD Current-mode output indicating a system status change to the next lower bq76PL536A
AUX 31 O Switched 1-mA limited output from REG50
BAT1 63 P Power-supply voltage, connect to most-positive cell +, tie to BAT2 on PCB
BAT2 64 P Power-supply voltage, connect to most-positive cell +, tie to BAT1 on PCB
CB1 12 O Cell-balance control output
CB2 10 O Cell-balance control output
CB3 8 O Cell-balance control output
(1) Key: I = digital input, AI = analog input, O = digital output, OD = open-drain output, T = 3-state output, P = power.
2 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
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