Datasheet

DRDY_N

I-to-V Conversion

CONVERT_END

CONVERT_START

DRDY_S

DRDY_H

V-to-I Conversion

DEVICE_STATUS[DRDY]

SET

CLR

bq76PL536A

SLUSAD3A –JUNE 2011–REVISED AUGUST 2012

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If the CONV_H pin is used in the design, it must be maintained in a default low state (~0 V) to allow use of the

ADC_CONVERT[CONV] bit to trigger ADC conversions. If the CONV pin is kept high, the

ADC_CONVERT[CONV] bit does not function, and device current consumption is increased by the signaling

current, ~900 µA. If the CONV_H pin is not used by the user’s design, the pin may be left floating; the internal

current sink to VSS maintains proper bias.

Firmware Start

The CONVERT_CTRL[CONV] bit is also used to initiate a conversion by writing a 1 to the bit. It is automatically

reset at the end of a conversion cycle. The bit may only be written to 1; the IC always resets it to 0. The

BROADCAST form of packet is recommended to start all device conversions simultaneously.

Designer Note: The external CONV_H (CONV_S) pin must be held in the de-asserted (=0) state to allow the

CONV register bit to initiate conversions. An internal pulldown is provided on the pin to maintain this state.

Data Ready

The bq76PL536A signals that data is ready when the last conversion data has been stored to the associated

data result register by asserting the DRDY_S pin (DRDY_H if HOST = 0) if the DRDY_N pin is also asserted.

DRDY_S (DRDY_H) signals are cleared on the next conversion start.

Figure 6. Data-Ready Logic

ADC Channel Selection

The ADC_CONTROL register can be configured as follows:

MEASUREMENT ADC_CONTROL

VCELL1 CELL_SEL = 0x00

VCELL1, VCELL2 CELL_SEL = 0x01

VCELL1, VCELL2, VCELL3 CELL_SEL = 0x02

VCELL1, VCELL2, VCELL3, VCELL4 CELL_SEL = 0x03

VCELL1, VCELL2, VCELL3, VCELL4, VCELL5 CELL_SEL = 0x04

VCELL1, VCELL2, VCELL3, VCELL4, VCELL5, VCELL6 CELL_SEL = 0x05

External thermistor input 1 TS1 = 1

External thermistor input 2 TS2 = 1

General-purpose analog input GPAI = 1

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