Datasheet

bq76PL536A
SLUSAD3A –JUNE 2011–REVISED AUGUST 2012 www.ti.com
Vertical Communications Bus
Typical values stated where T
A
= 25ºC and V
BAT
= 20 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
HV_SCLK
Propagation delay, SCLK_H to HOST = 0 40 ns
SCLK_N
t
VB_SCLK
Propagation delay, SCLK_S to HOST = 1 30 ns
SCLK_N
t
HV_CS
Propagation delay, CS_H to CS_N HOST = 0 40 ns
t
VB_CS
Propagation delay, CS_S to CS_N HOST = 1 30 ns
t
HV_SDI
Propagation delay, SDI_H to SDI_N HOST = 0 40 ns
t
VB_SDI
Propagation delay, SDI_S to SDI_N HOST = 1 30 ns
t
HV_CONV
Propagation delay, CONV_H to HOST = 0 100 ns
CONV_N
t
VB_CONV
Propagation delay, CONV_S to HOST = 1 30 ns
CONV_N
t
HV_SDO
Propagation delay, SDO_N to HOST = 0 10 ns
SDO_H
t
VB_SDO
Propagation delay, SDO_N to HOST = 1 40 ns
SDO_S
t
HV_DRDY
Propagation delay, DRDY_N to HOST = 0 60 ns
DRDY_H
t
VB_DRDY
Propagation delay, DRDY_N to HOST = 1 40 ns
DRDY_S
t
HV_FAULT
Propagation delay, FAULT_N to HOST = 0 55 ns
FAULT_H
t
VB_FAULT
Propagation delay, FAULT_N to HOST = 1 30 ns
FAULT_S
t
HV_ALERT
Propagation delay, ALERT_N to HOST = 0 65 ns
ALERT_H
t
VB_ALERT
Propagation delay, ALERT_N to HOST = 1 30 ns
ALERT_S
(1) Typical values are quoted in place of MIN/MAX for design guidance only. Actual propagation delay depends heavily on wiring and
capacitance in the signal path. These parameters are not tested in production due to these dependencies on system design
considerations.
ANALOG-TO-DIGITAL CONVERSION (ADC)
General Features
The integrated 14-bit (unsigned) high-speed successive approximation register (SAR) analog-to-digital converter
uses an integrated band-gap reference voltage (V
REF
) for the cell and brick measurements. The ADC has a front-
end multiplexer for nine inputs – six cells, two temperature sensors, and one general-purpose analog input
(GPAI). The GPAI input can further be multiplexed to measure the brick voltage between the BATx pin and VC0
or the voltage between the GPAI+ and GPAI– pins.
The ADC and reference are factory trimmed to compensate for gain, offset, and temperature-induced errors for
all inputs. The measurement result is not allowed to roll over due to offset error at the top and bottom of the
range, i.e., a reading near zero does not underflow to 0x03ff due to offset error, and vice-versa.
The converter returns 14 valid unsigned magnitude bits in the following format:
<00xxxxxx xxxxxxxx>
Each word is returned in big-endian format in a register pair consisting of two adjacent 8-bit registers. The MSB
of the word is located in the lower-address register of the pair, i.e., data for cell 1 is returned in registers 0x03
and 0x04 as 00xxxxxx xxxxxxxxb.
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