Datasheet

t
CS,LEAD
CS
t
CS,LAG
t
(SCLK )
SCLK
t
(HIGH)
t
(LOW)
SDI
t
SU,SDI
t
HD,SDI
SDO
t
ACC
t
VALID, SDO
t
DIS
t
CS _ DLY
bq76PL536A
www.ti.com SLUSAD3A –JUNE 2011–REVISED AUGUST 2012
AC TIMING CHARACTERISTICS
SPI DATA INTERFACE
Typical values stated where T
A
= 25°C and V
BAT
= 20 V, Min/Max values stated where T
A
= –40˚C to 85°C and V
BAT
= 7.2 V
to 27 V (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
f
SCLK
SCLK frequency
(1)
10 250 1000 kHz
SCLK
DC
SCLK_H duty cycle, t
(HIGH)
/ t
(SCLK)
or t
(LOW)
/ t
(SCLK)
40% 60%
t
CS,LEAD
CS_H lead time, CS_H low to clock 50 SCLK/2 ns
t
CS,LAG
CS_H lag time. Last clock to CS_H high 10 SCLK/2 ns
t
CS,DLY
CS_H high to CS_H low (inter-packet delay requirement) 3 µs
t
ACC
CS_H access time
(2)
: CS_H low to SDO_H data out 125 250 ns
CS_H disable time
(2)
: CS_H high to SDO_H high
t
DIS
2.5 2.7 µs
impedance
t
SU,SDI
SDI_H input-data setup time 15 ns
t
HD,SDI
SDI_H input-data hold time 10 ns
SDO_H output-data valid time
t
VALID,SDO
C
L
≤ 20 pF 75 110 ns
SCLK_H edge to SDO_H valid
(1) Maximum SCLK frequency is limited by the number of bq76PL536A devices in the vertical stack. The maximum listed here may not be
realizable in systems due to delays and limits imposed by other components including wiring, connectors, PCB material and routing, etc.
See text for details.
(2) Time listed is for single device.
Figure 3. SPI Host Interface Timing
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