Datasheet

SCL
SDA
SDA
SCL
SDA
SCL
bq76925
www.ti.com SLUSAM9B –JULY 2011– REVISED DECEMBER 2011
I
2
C Compatible Interface
DC PARAMETERS MIN TYP MAX UNIT
V
IL
Input Low Logic Threshold 0.6 V
V
IH
Input High Logic Threshold 2.8 V
V
OL
Output Low Logic Drive I
OL
= 1 mA 0.20 V
I
OL
= 2.5 mA 0.40
V
OH
Output High Logic Drive (Not applicable due to open-drain outputs) N/A V
I
LKG
I
2
C Pin Leakage Pin = 5.0 V, Output in high-Z < 1 µA
AC PARAMETERS
t
r
SCL, SDA Rise Time 1000 ns
t
f
SCL, SDA Fall Time 300 ns
t
w(H)
SCL Pulse Width High 4.0 µs
t
w(L)
SCL Pulse Width Low 4.7 µs
t
su(STA)
Setup time for START condition 4.7 µs
t
h(STA)
START condition hold time after which first clock pulse is generated 4.0 µs
t
su(DAT)
Data setup time 250 ns
t
h(DAT)
Data hold time 0
(1)
µs
t
su(STOP)
Setup time for STOP condition 4.0 µs
t
su(BUF)
Time the bus must be free before new transmission can start 4.7 µs
t
V
Clock Low to Data Out Valid 900 ns
t
h(CH)
Data Out Hold Time After Clock Low 0 ns
f
SCL
Clock Frequency 0 100 kHz
t
WAKE
I2C ready after transition to Wake Mode 2.5 ms
(1) Devices must provide internal hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL.
Figure 1. I
2
C Timing
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