Datasheet
bq76925
www.ti.com
SLUSAM9B –JULY 2011– REVISED DECEMBER 2011
Register Map
Address Name Access D7 D6 D5 D4 D3 D2 D1 D0
0x00 STATUS R/W ALERT CRC_ERR POR
0x01 CELL_CTL R/W VCOUT_SEL CELL_SEL
0x02 BAL_CTL R/W BAL_6 BAL_5 BAL_4 BAL_3 BAL_2 BAL_1
0x03 CONFIG_1 R/W I_THRESH I_COMP_POL I_AMP_CAL I_GAIN
0x04 CONFIG_2 R/W CRC_EN REF_SEL
0x05 POWER_CTL R/W SLEEP SLEEP_DIS I_COMP_EN I_AMP_EN VC_AMP_EN VTB_EN REF_EN
0x06 Reserved R/W
0x07 CHIP_ID RO CHIP_ID
0x08 – 0x0F Reserved R/W
0x10 VREF_CAL EEPROM VREF_OFFSET_CORR VREF_GAIN_CORR
0x11 VC1_CAL EEPROM VC1_OFFSET_CORR VC1_GAIN_CORR
0x12 VC2_CAL EEPROM VC2_OFFSET_CORR VC2_GAIN_CORR
0x13 VC3_CAL EEPROM VC3_OFFSET_CORR VC3_GAIN_CORR
0x14 VC4_CAL EEPROM VC4_OFFSET_CORR VC4_GAIN_CORR
0x15 VC5_CAL EEPROM VC5_OFFSET_CORR VC5_GAIN_CORR
0x16 VC6_CAL EEPROM VC6_OFFSET_CORR VC6_GAIN_CORR
0x17 VC_CAL_EXT_1 EEPROM VC1_OC_4 VC1_GC_4 VC2_OC_4 VC2_GC_4
0x18 VC_CAL_EXT_2 EEPROM VC3_OC_4 VC3_GC_4 VC4_OC_4 VC4_GC_4 VC5_OC_4 VC5_GC_4 VC6_OC_4 VC6_GC_4
0x10 – 0x1A Reserved EEPROM
0x1B VREF_CAL_EXT EEPROM 1 VREF_OC_5 VREF_OC_4 VREF_GC_4
0x1C – 0x1F Reserved EEPROM
Register Descriptions
STATUS
Address Name Type D7 D6 D5 D4 D3 D2 D1 D0
0x00 STATUS R/W ALERT CRC_ERR POR
Defaults: 0 0 0 0 0 0 0 1
ALERT: Over-current alert. Reflects state of the over-current comparator. ‘1’ = over-current.
CRC_ERR: CRC error status. Updated on every I
2
C write packet when CRC_EN = ‘1’. ‘1’ = CRC error.
POR: Power on reset flag. Set on each power-up and wake-up from sleep. May be cleared by writing with ‘0’.
CELL_CTL
Address Name Type D7
(1)
D6 D5 D4 D3 D2 D1 D0
0x01 CELL_CTL R/W VCOUT_SEL CELL_SEL
Defaults: 0 0 0 0 0
(1) This bit must be kept = 0
VCOUT_SEL: VCOUT MUX select. Selects the VCOUT pin function as follows.
VCOUT_SEL VCOUT
0 0 VSS
0 1 VCn (n determined by CELL_SEL)
1 0 VREF × 0.5
1 1 VREF × 0.85
CELL_SEL: Cell select. Selects the VCn input for output on VCOUT when VCOUT_SEL = ‘01’.
VCOUT_SEL CELL_SEL VCOUT
0 1 0 0 0 VC1
0 1 0 0 1 VC2
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