Datasheet

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Circuit Details and Configuration

Table 7. J3, V3P3 Pin Circuit Configuration

Header Name Position Purpose

1 - 2 External V3P3 source in circuit (default).

OFF External V3P3 source in circuit

Table 8. J4, V3P3 Pin Capacitor Circuit Configuration

Header Name Position Purpose

1 - 2 External V3P3 source in circuit 1-µF + 4.7-µF

capacitance used (default).

OFF Internal V3P3 source in circuit and 1-µF capacitance

used

Table 9. J5, SENSEP Pin Circuit Configuration

Header Name Position Purpose

1 - 2 SENSEP connected to sense resistor for normal operation

(default).

OFF SENSEP disconnected from sense resistor. This is a test mode

operation where a mV source is applied to J5:pin 1 for simulation

of current.

Table 10. J6, DVCC Pin Circuit Configuration

Header Name Position Purpose

1 - 2 Power to MSP430 during programming is from VCC-Tool. (default)

2 - 3 Power to MSP430 during programming is from VCC-Target.

2.2.1 Cell Simulator DIP Switch (S4)

The eight-position DIP switch (S4) allows the user to simulate cell-voltage inputs to the bq76925 rather

than supply actual cell voltages. See Table 11 for details of the operation of the DIP switch.

CAUTION

Use silkscreen labeling and square pin 1 pad to determine orientation and

operation of the eight-position DIP switch. Ignore numbers actually printed on

the switch.

All S4 dip switches must be opened when using a battery with the EVM.

Table 11. DIP Switch, S4

Switch Terminal Label Purpose

Name

S4 1 Battery Switch to connect power supply to resistor network. Closure

activates LED D13.

2 Cell 6 Applies simulated cell voltage to VC6.

3 Cell 5 Applies simulated cell voltage to VC5.

4 Cell 4 Applies simulated cell voltage to VC4.

5 Cell 3 Applies simulated cell voltage to VC3.

6 Cell 2 Applies simulated cell voltage to VC2.

7 Cell 1 Applies simulated cell voltage to VC1.

8 Cell 0 Applies simulated cell voltage to VC0.

SLUU514–July 2011 bq76925EVM Evaluation Module

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