Datasheet

60.0
70.0
80.0
90.0
100.0
0.0 1.0 2.0 3.0 4.0 5.0 6.0
Output Power (W)
Efficiency (%)
Full Sync Mode Enabled
70.0
80.0
90.0
100.0
1.0 2.0 3.0 4.0 5.0
Output Power (W)
Efficiency (%)
bq51011
bq51013
www.ti.com SLVSAT9D –APRIL 2011–REVISED AUGUST 2012
PIN FUNCTIONS (continued)
NAME YFF RHL I/O DESCRIPTION
I/O Programming pin for the over current limit. Connect external resistor to
ILIM G1 12 V
SS
. Size R
ILIM
with the following equation: R
ILIM
= 300 / I
( max)
where
I
(max)
is the desired current limit for the power supply.
Connect this pin to the wired adapter input. When a voltage is applied to
this pin wireless charging is disabled and AD-EN is driven low. Connect to
AD G4 9 I
GND through a 1µF capacitor. If unused, capacitor is not required and
should be grounded directly.
Push-pull driver for external PFET connecting AD and OUT. This node is
pulled to the higher of OUT and AD when turning off the external FET.
AD-EN F3 8 O This voltage tracks approximately 4V below AD when voltage is present
at AD and provides a regulated VSG bias for the external FET. Float this
pin if unused.
Must be connected to ground and pulled up to VTSB via two series
resistors. If an NTC function is not desired, size R2 to be twice that of R3.
TS/CTRL F1 13 I As a CTRL pin pull to ground to send End Power/Temperature Fault
message to the transmitter, pull-up to send End Power/Termination
message to the transmitter.
EN1 G3 10 I Inputs that allow user to enable/disable wireless and wired charging <EN1
EN2>
<00> wireless charging is enabled unless the AD voltage is > 3.6 V.
<01> AD mode is disabled, wireless charging enabled.
EN2 G2 11 I
<10> AD-EN pulled low, wireless charging disabled.
<11> wired and wireless charging disabled.
2.2V LDO that periodically biases the TS/CTRL resistor network. Connect
VTSB F2 14 O
to TS/CTRL via a resistor
Open-drain output – active when output current is being delivered to the
CHG F4 7 O
load (i.e. when the output of the supply is enabled).
Spacer
TYPICAL CHARACTERISTICS
Figure 4. Rectifier Efficiency Figure 5. IC Efficiency from AC Input to DC Output
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