Datasheet

24ms
35 or 235ms
10ms deglitch on all TS
comps – read for TS
fault. Hold TS_OPEN
comp in reset.
Hold TS comps in reset.
Read TS_DRIVEN with
10-ms deglitch.
TS_READ
20
25
30
35
40
45
50
55
0 10 20 30 40 50 60
Temperature (°C)
Vtsb Ratio (%)
bq51011
bq51013
www.ti.com SLVSAT9D –APRIL 2011–REVISED AUGUST 2012
• R3 = 13.98kΩ
where:
• T
COLD
= 0°C
• T
HOT
= 60°C
• β = 4500
• R
O
= 10kΩ
The plot of the percent V
TSB
vs. temperature is shown in Figure 28:
Figure 28. Example Solution for an NTC resistor with R
O
= 10KΩ and β = 4500
Figure 29 illustrates the periodic biasing scheme used for measuring the TS state. The TS_READ signal enables
the TS bias voltage for 24ms. During this period the TS comparators are read (each comparator has a 10 ms
deglitch) and appropriate action is taken based on the temperature measurement. After this 24ms period has
elapsed, the TS_READ signal goes low, which causes the TS-Bias pin to become high impedance. During the
next 35ms (priority packet period) or 235ms (standard packet period), the TS voltage is monitored and compared
to 100mV. If the TS voltage is greater than 100mV then a secondary device is driving the TS/CTRL pin and a
CTRL = ‘1’ is detected.
Figure 29. Timing Diagram for TS Detection Circuit
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