Datasheet

t
SU(STA)
SCL
SDA
t
w(H)
t
w(L)
t
f
t
r
t
(BUF)
t
r
t
d(STA)
REPEATED
START
t
h(DAT)
t
su(DAT)
t
f
t
su(STOP)
STOP START
t
(B)
t
(BR)
t
(HW1)
t
(HW0)
t
(CYCH)
t
(DW1)
t
(DW0)
t
(CYCD)
Break
7-bitaddress
8-bitdata
(a) BreakandBreakRecovery
(c) Host TransmittedBit
(d) Gauge TransmittedBit
(e) GaugetoHostResponse
1.2V
t
(RISE)
(b) HDQlinerisetime
1-bit
R/W
t
(RSPS)
bq34z100
SLUSAU1B –MAY 2012–REVISED DECEMBER 2012 www.ti.com
Figure 3. Timing Diagrams
I
2
C-COMPATIBLE INTERFACE TIMING CHARACTERISTICS
T
A
= –40°C to 85°C, C
REG
= 0.47 μF, 2.45 V < V
REGIN
= V
BAT
< 5.5 V; typical values at T
A
= 25°C and V
REGIN
= V
BAT
= 3.6 V
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
r
SCL/SDA rise time 300 ns
t
f
SCL/SDA fall time 300 ns
t
w(H)
SCL pulse width (high) 600 ns
t
w(L)
SCL pulse width (low) 1.3 μs
t
su(STA)
Setup for repeated start 600 ns
t
d(STA)
Start to first falling edge of SCL 600 ns
t
su(DAT)
Data setup time 100 ns
t
h(DAT)
Data hold time 0 ns
t
su(STOP)
Setup time for stop 600 ns
t
BUF
Bus free time between stop and start 66 μs
f
SCL
Clock frequency 400 kHz
Figure 4. I
2
C-Compatible Interface Timing Diagrams
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