Datasheet

100
VCELL1
VCELL2
OUT
VDD
VSS
0.1
0.1µF
1k
1k
bq2945xy
Pack +
Pack
V3
V2
V1
PWRPAD
µF
0.1
µF
VCELL1
VCELL3
VCELL2
OUT
VDD
VSS
RIN
bq2945xy
Pack +
Pack
V
3
V2
V1
RIN
RIN
CIN
CIN
CIN
CVD
RVD
PWRPAD
bq294502, bq294504, bq294512, bq294515
bq294522, bq294524, bq294532, bq294562
bq294572, bq294582, bq294592
SLUSAJ3C SEPTEMBER 2011REVISED MAY 2012
www.ti.com
APPLICATION INFORMATION
Figure 7. Application Configuration
Changes to the ranges stated in Table 1 will impact the accuracy of the cell measurements. Figure 7 shows each
external component.
Table 1. Parameters
PARAMETER External Component MIN NOM MAX UNIT
Voltage monitor filter resistance RIN 900 1000 1100 Ω
Voltage monitor filter capacitance CIN 0.01 0.1 µF
Supply voltage filter resistance RVD 100 1K Ω
Supply voltage filter capacitance CVD 0.1 µF
APPLICATION SCHEMATIC
Figure 8. 3-Series Cell Configuration with Fixed Figure 9. 2-Series Cell Configuration with Internal
Delay Fixed Delay
CUSTOMER TEST MODE
Customer Test Mode (CTM) helps to reduce test time for checking the overvoltage delay timer parameter once
the circuit is implemented in the battery pack. To enter CTM, VDD should be set to at least 10 V higher than V3
(see Figure 10). The delay timer is greater than 10 ms, but considerably shorter than the timer delay in normal
operation. To exit Customer Test Mode, remove the VDD to VC3 voltage differential of 10 V so that the decrease
in this value automatically causes an exit.
CAUTION
Avoid exceeding any Absolute Maximum Voltages on any pins when placing the part
into Customer Test Mode. Also avoid exceeding Absolute Maximum Voltages for the
individual cell voltages (V3–V2), (V2–V1), and (V1–VSS). Stressing the pins beyond
the rated limits may cause permanent damage to the device.
8 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): bq294502 bq294504 bq294512 bq294515 bq294522 bq294524 bq294532 bq294562
bq294572 bq294582 bq294592