Datasheet
www.ti.com
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
BAT
DSG
VC1
VC2
VC3
VC4
VC5
SR1
SR2
WDI
CELL
GND
OD
PMS
PACK
ZVCHG
CHG
SLEEP
REG
TOUT
XALERT
GND
SDATA
SCLK
PW PACKAGE
(TOP VIEW)
BAT
DSG
VC1
VC3
VC4
SR2
SR1
VC5
GND
XALERT
REG
TOUT
ZVCHG
PACK
OD
WDI
CELL
SDATA
GND
VC2
SCLK
SLEEP
CHG
PMS
RTH PACKAGE
(TOP VIEW)
bq29312A
SLUS629A – JANUARY 2005 – REVISED AUGUST 2005
Terminal Functions
TERMINAL
PIN NO. DESCRIPTION
NAME
RTH PW
BAT 22 1 Diode protected BAT+ terminal and primary power source.
DSG 23 2 Push-pull output discharge FET gate drive
VC1 24 3 Sense voltage input terminal for most-positive cell and balance current input for most-positive cell.
Sense voltage input terminal for second most-positive cell, balance current input for second most-positive cell
VC2 1 4
and return balance current for most-positive cell.
Sense voltage input terminal for third most-positive cell, balance current input for third most-positive cell and
VC3 2 5
return balance current for second most-positive cell.
Sense voltage input terminal for least-positive cell, balance current input for least-positive cell and return
VC4 3 6
balance current for third most-positive cell.
VC5 4 7 Sense voltage input terminal for most-negative cell, return balance current for least-positive cell.
SR1 5 8 Current sense positive terminal when charging relative to SR2
SR2 6 9 Current sense negative terminal when discharging relative to SR2 current sense terminal
WDI 7 10 Digital input that provides the timing clock for the OC and SC delays and also acts as the watchdog clock.
CELL 8 11 Output of scaled value of the measured cell voltage.
GND 9 12 Analog ground pin and negative pack terminal
SCLK 10 13 Open-drain bidirectional serial interface clock with internal 10-k Ω pullup to V
(REG)
.
SDATA 11 14 Open-drain bidirectional serial interface data with internal 10-k Ω pullup to V
(REG)
.
GND 12 15 Connect to GND
XALERT 13 16 Open-drain output used to indicate status register changes. With internal 100-k Ω pullup to V
(REG)
TOUT 14 17 Provides thermistor bias current
REG 15 18 Integrated 3.3-V regulator output
SLEEP 16 19 This pin is pulled up to V
(REG)
internally, open or H level makes Sleep mode
CHG 17 20 Push-pull output charge FET gate drive
ZVCHG 18 21 The ZVCHG FET drive is connected here
PACK 19 22 PACK positive terminal and alternative power source
PMS 20 23 0-V charge configuration select pin, CHG terminal ON/OFF is determined by this pin.
OD 21 24 NCH FET open-drain output
7