Datasheet

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PACK
ZVCHG
PMS
REG
CHG
DSG
BAT
4.7 mF
Battery
DSG-FET CHG-FET
Pack+
I
(ZVCHG)
I
(FASTCHG)
CV
CC
Charger
DC Input
bq29312A
I
(ZVCHG)
= 0 V Precharge Current
I
(FASTCHG)
= Fast Current
OD
NC
bq29312A
SLUS629A – JANUARY 2005 – REVISED AUGUST 2005
APPLICATION INFORMATION (continued)
The disadvantages is that during 0-V charging, bq29312A is inactive. The device does not protect the battery
and does not update battery information (now is 0 V charging) to the PC.
There are two advantage of this configuration:
1. The voltage between BAT and PACK is lower. Higher precharge current is allowed due to less heat loss in
the FET, and no external resistor is required.
2. The charge FET is turned on during precharging. The precharge current can be fully controlled by the
charger.
Figure 11. Common FET Mode Circuit Diagram
The signal timing during the common FET mode is shown in Figure 12 . The CHG-FET is turned on when the
charger is connected. As V
(BAT)
rises and V
(PACK)
reaches the bq29312A minimum supply voltage, the REG
output becomes active and the host controller starts to work.
When V
(PACK)
becomes high enough, the host controller turns ON the DSG-FET. The charger enters the fast
charging mode when V
(BAT)
reaches the fast charge level.
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