Datasheet

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t - Time - mS
Voltage - V
0 4 8 12 16
4
20
10
0
8
2
6
14
18
12
16
20
V
(PACK)
3.5 V
V
(ZVCHG)
=
V
(PACK)
- 8 V
V
(ZVCHG)
= V
(PACK)
/ 2
V
(BAT)
bq29312A
SLUS629A – JANUARY 2005 – REVISED AUGUST 2005
APPLICATION INFORMATION (continued)
Figure 9. Voltage Transition at ZVCHG, PACK, and BAT
As V
(PACK)
exceeds 7 V, V
(ZVCHG)
= V
(PACK)
/2. However, V
(ZVCHG)
is maintained to limit the voltage between PACK
and ZVCHG at a maximum of 8 V(typ). This limitation is intended to avoid excessive voltage between the gate
and the source of ZVCHG-FET.
The signal timing is shown in Figure 10 . When precharge begins, (V
(BAT)
= 0 V) V
(PACK)
is clamped to 3.5 V and
holds the supply voltage for bq29312A operation. After V
(BAT)
reaches sufficient voltage high enough for
bq29312A operation, the CHG-FET and the DSG-FET are turned ON and ZVCHG-FET is turned OFF.
Although the current path is changed, the same precharging current is still applied. When V
(BAT)
reaches the fast
charging voltage (typical 3 V per cell), the charger switches into fast charging mode.
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