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FUNCTION CTL: Function Control Register

CELL SEL: Cell Select Register

bq29312A

SLUS629A – JANUARY 2005 – REVISED AUGUST 2005

FUNCTION CTL REGISTER (0x03)

7 6 5 4 3 2 1 0

0 0 TOUT XSCD SSCC XOL PACKOUT VMEN

The FUNCTION CTL register enables and disables functions of the bq29312A.

FUNCTION CTL b0 (VMEN): This bit enables or disables the cell and battery voltage monitoring function.

0 = disable voltage monitoring (default). CELL output is pulled down to GND level.

1 = enable voltage monitoring.

FUNCTION CTL b1 (PACKOUT): This bit is used to translate the PACK input to the CELL pin when VMEN=1.

The pack voltage is divided by 25 and is presented on CELL regardless of the CELL_SEL register settings.

0 = disable PACK OUT (default).

1 = enable PACK OUT.

FUNCTION CTL b2 (XOL): This bit enables or disables the overcurrent sense function.

0 = enable overload sense (default).

1 = disable overload sense.

FUNCTION CTL b3 (XSCC): This bit enables or disables the short current sense function of charging.

0 = enable short-circuit current sense in charge direction (default).

1 = disable short-circuit current sense in charge direction.

FUNCTION CTL b4 (XSCD): This bit enables or disables the short current sense function of discharge.

0 = enable short-circuit current sense in discharge direction (default).

1 = disable short-circuit current sense in discharge direction.

FUNCTION CTL b5 (TOUT): This bit controls the power to the thermistor.

0 = thermistor power is off (default).

1 = thermistor power is on.

CELL_SEL REGISTER (0x04)

7 6 5 4 3 2 1 0

CB3 CB2 CB1 CB0 CAL1 CAL0 CELL1 CELL0

This register determines cell selection for voltage measurement and translation, cell balancing, and the

operational mode of the cell voltage monitoring.

CELL_SEL b0–b1 (CELL0–CELL1): These two bits select the series cell for voltage measurement translation.

CELL1 CELL0 SELECTED CELL

0 0 VC4–VC5, Bottom series element (default)

0 1 VC4–VC3, Second lowest series element

1 0 VC3–VC2, Second highest series element

1 1 VC1–VC2, Top series element

CELL_SEL b2–b3 (CAL1, CAL0): These bits determine the mode of the voltage monitor block.

CAL1 CAL0 SELECTED MODE

0 0 Cell translation for selected cell (default)

0 1 Offset measurement for selected cell

1 0 Monitor the V

REF

value for gain calibration

1 1 Monitor the V

REF

directly value for gain calibration, bypassing the translation circuit