Datasheet

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STATUS : Status register

OUTPUT CTL: Output Control Register

bq29312A

SLUS629A – JANUARY 2005 – REVISED AUGUST 2005

The bq29312A has nine addressable registers. These registers provide status, control, and configuration

information for the battery protection system.

Table 3. Addressable Registers

NAME ADDR TYPE DESCRIPTION

STATUS 0x00 R Status register

OUTPUT CTL 0x01 R/W Output pin control from system host

STATE CTL 0x02 R/W State control

FUNCTION CTL 0x03 R/W Function control

CELL _SEL 0x04 R/W Battery cell select for cell translation and balance bypass and select mode for calibration

OLV 0x05 R/W Overload threshold voltage

OLT 0x06 R/W Overload delay time

SCC 0x07 R/W Short-circuit current threshold voltage and delay for charge

SCD 0x08 R/W Short-circuit current threshold voltage and delay for discharge

STATUS REGISTER (0x00)

7 6 5 4 3 2 1 0

0 0 ZVCLMP SLEEPDET WDF OL SCCHG SCDSG

The STATUS register provides information about the current state of the bq29312A. Reading the STATUS

STATUS b0 (SCDSG): This bit indicates a short-circuit in the discharge direction.

0 = Current below the short-circuit threshold in the discharge direction (default).

1 = Current greater than or equal to the short-circuit threshold in the discharge direction.

STATUS b1 (SCCHG): This bit indicates a short-circuit in the charge direction.

0 = Current below the short-circuit threshold in the charge direction (default).

1 = Current greater than or equal to the short-circuit threshold in the charge direction.

STATUS b2 (OL): This bit indicates an overload condition.

0 = Current less than or equal to the overload threshold (default).

1 = Current greater than overload threshold.

STATUS b3 (WDF): This bit indicates a watchdog fault condition has occurred.

0 = 32-kHz oscillation is normal (default).

1 = 32-kHz oscillation stopped or not started and the watchdog has timed out.

STATUS b4 (SLEEPDET): This bit indicates the bq29312A is SLEEP mode.

0 = bq29312A is not in SLEEP mode (default).

1 = bq29312A is in SLEEP mode.

STATUS b5 (ZVCLMP): This bit indicates ZVCHG output is clamped.

0 = ZVCHG pin is not clamped (default).

1 = ZVCHG pin is clamped.

OUTPUT CTL REGISTER (0x01)

7 6 5 4 3 2 1 0

0 0 0 OD XZVCHG CHG DSG LTCLR