Datasheet

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Precharge and 0-V Charging—Theory of Operation
SLEEP Control Input (SLEEP)
Power Modes
bq29312A
SLUS629A – JANUARY 2005 – REVISED AUGUST 2005
FUNCTIONAL DESCRIPTION (continued)
The default-state of the CHG and DSG FET drive is off, when PMS = GND. A host can control the FET drive by
programming OUTPUT CTL (b3...b1) where b1 is used to control the discharge FET, b2 is used to control the
charge FET, and b3 is used to control the ZVCHG FET. These controls are only valid when not in the initialized
state. The CHG drive FET can be powered by PACK and the DSG FET can be powered by BAT.
The bq29312A supports both a charger that has a precharge mode and one that does not. The bq29312A also
supports charging even when the battery falls to 0 V. Detail is described in the application section.
The SLEEP input is pulled-up internally to REG. When SLEEP is pulled to REG, the bq29312A enters the
SLEEP mode. The SLEEP mode disables all the FET outputs and the OL, SC, and watchdog faults are also
disabled. The RAM configuration is still valid on exit of the SLEEP mode. The host can force the bq29312A into
SLEEP mode via register control also.
Table 1. SLEEP Control Input
SLEEP
ITEM EXIT SLEEP
FUNCTION I
2
C READ/WRITE
I
2
C Read/Write Active
REG Output Active
External pin control:
CHG, DSG, ZVCHG, TOUT, OD
OC and SC protection:
Write is available, Last pre-sleep entry configuration is valid. (If
SCD, SCC and OCD
but read is disabled change configuration, latest write data is valid.)
CELL Translation Disabled
PACKOUT, VMEN
Cell Balancing:
CB[3:0]
Watchdog: WDDIS
The bq29312A has three power modes, Normal, Sleep, and Ship. The following table outlines the operational
functions during these power modes.
Table 2. Power Modes
POWER TO EXIT POWER
TO ENTER POWER MODE MODE DESCRIPTION
MODE MODE
The battery is in normal operation with protection, power
management, and battery monitoring functions available and
SLEEP = GND and
operating.
Normal STATE CTL( b0) = 0 and
STATE CTL( b1) = 0
The supply current of this mode varies as the host can enable
and disable various power management features.
All functions stop except LDO and I
2
C interface.
{SLEEP = REG (floating) or On entry to this mode, all registers are masked off keeping
SLEEP = GND and
Sleep STATE CTL( b0) = 1 } and their state.
STATE CTL( b0) = 0
STATE CTL( b1) = 0
The host controller can change the RAM registers via the I
2
C
interface, but reading data is disabled until exit of Sleep mode.
STATE CTL( b1) = 1 The bq29312A is completely shut down as in the sleep mode.
Supply voltage to
Ship And supply at the PACK pin is In addition, the REG output is disabled, I
2
C interface is
PACK
removed powered down, and memory is not valid.
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